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MODERN ENIAC WP2 Meeting

MODERN ENIAC WP2 Meeting. WP2 Tasks review summary Catania, 2010 Nov. 09-10. Contents. WP2 Task 2.1 to 2.5 summary Matrix, Gantt chart, relation with other Wps Action points from meeting. WP2: Relationship among work packages. 3. WP2 Objectives. Objectives

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MODERN ENIAC WP2 Meeting

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  1. MODERN ENIAC WP2 Meeting WP2 Tasks review summary Catania, 2010 Nov. 09-10 Project Review Meeting Catania, Nov.09-10, 2010

  2. Contents • WP2 • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010

  3. WP2: Relationship among work packages MODERN General Meetings Catania, Nov. 9 & 10, 2010 3

  4. WP2 Objectives • Objectives • Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation • Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non-silicon technologies • Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies Project Review Meeting Catania, Nov 09-10, 2010

  5. WP2 Key Figures 5 Tasks/18 deliverables (reports): Process (2) & device (6) simulation Electrical characterization (4) & Reliability(3) Compact modeling (3) Covering both Tools/Methodology improvements and Application results Wide spectrum of technologies & devices applications 45nm: planar Mosfet 32nm: planar Mosfet, FinFet 22nm: FD SOI Mosfet State-of-art NVM Discrete Power Device, SiC, GaN/AlGaN HV CMOS TOTAL EFFORT: 638.6 PM =53.22 PY Reference: MODERN Rev2.1.7 project description Project Review Meeting Catania, Nov.09-10, 2010 18/09/2014 5

  6. WP2 meetingDomain overview per task and partner • PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). • Significant communalities of technology targets, except different ones for Process and Device simulation. • (not funded) MODERN General Meetings Catania, Nov. 9 & 10, 2010

  7. WP2 Task Definition and Contributors Project Review Meeting Catania, Nov.09-10, 2010 18/09/2014 7

  8. WP2 Task Leaders 18/09/2014 8

  9. Contents • WP2 introduction • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010

  10. MODERN General MeetingTask 2.1 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010

  11. Process simulation: T2.1 Deliverables Task Leader: valeria.cinnera@st.com 18/09/2014 11

  12. Process recipes Process flow Virtual device High Level factory Specific process conditions TCAD Experiments Mask Layout FAB1 PCM PCM Process Compact model derived from TCAD Technology transferred to FAB2 using PCM FAB2 ST-I WP2 Activity MODERN General Meetings Catania, Nov. 9 & 10, 2010

  13. PCM approach PCM STUDIO EHD5 SEMICELL • Synopsys platform: • Sentaurus and PCM Studio • Simulation of Power-Mos semi cell with the nominal values of the process input parameters SENTAURUS WORKBENCH DOE PCM • Parameter screening to identify the process parameters that • have an important impact on target electrical parameters. • Parameterized simulation setup (DOE) generating several simulation runs. • Device simulations of breakdown and I-V characteristic for each experiment. • Extraction of RSM model of device characteristics as function of process parameters using PCM Studio. MODERN General Meetings Catania, Nov. 9 & 10, 2010 13

  14. Process Variation at AMS - TUW • Process Flow Parameters Correlation Interface between commercial Synopsys Process Simulator and Minimos Device Simulator Sentaurus Work Bench Parameter Extraction Minimos MODERN General Meetings Catania, Nov. 9 & 10, 2010

  15. WP2 T2.1 action items • Task 2.1: Process simulation • D2.1.2 (M27): «  Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) » • AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2 Project Review Meeting Catania, Nov 09-10, 2010

  16. MODERN General MeetingTask 2.2 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010

  17. Device Simulation: T2.2 Deliverables Task Leader: a.asenov@elec.gla.ac.uk 18/09/2014 17

  18. T2.2.2 Overview VD=1.0V VD=50mV VD=50mV VD=1.0V 18/09/2014 18

  19. T2.2.2 Overview (Synopsys) (UNET-Università di Udine) 18/09/2014 18/09/2014 18/09/2014 19

  20. T2.2.2 Overview (UNET-Università di Bologna) 18/09/2014 18/09/2014 18/09/2014 20

  21. T2.2.3 Overview RDD LER LWR OTF PSG ITC 18/09/2014 21

  22. T2.2.3 Overview Flat AA &FG Rounded AA & FG 18/09/2014 22

  23. T2.2 action items • Task 2.2: Device simulation • D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET)” • AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL-UNET-SNPS-POLI-ST applies. • D2.2.5 (M27): « TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)” => AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011. • D2.2.6 (M36): « Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) . Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)” => AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox Project Review Meeting Catania, Nov 09-10, 2010

  24. MODERN General MeetingTask 2.3 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010

  25. Electrical Characterization: T2.3 Deliverables Task Leader: hans.tuinhout@nxp.com Project Review Meeting Crolles, June 22, 2009 Project Review Meeting Crolles, June 22, 2009 18/09/2014 25

  26. Task T2.3 D2.3.1: Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (ST, IMEP, UNGL) • Example of 45nm Nmos with pocket implants: • Conventional DOE and electrical characterization technique • Geometry scaling on transistor area impacted by Lateral doping gradient • Compact analytical model developed with 3 channel regions wi/wo pockets explains qualitative trend of Lscaling for VT mismatch • UNGL 3D simulation (D2.2.2) in line with experiments MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 22, 2010 26 26

  27. Task T2.3 D2.3.1: Experimental characterization of NVM devices (41nm, xGbits )in the presence of PV (NMX) • Neutral device scaling: • Local random variations for W,L, Oxide, Interpoly dielectric, RDD fluctuations (top) • Local systematic: Cell to cell interference (bottom) • After programming: • Local random • Local systematic VT Shift induced by neighbouring cells (top), or string series resistances (bottom) MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 22, 2010 27 27

  28. Task T2.3 D2.3.1: First PV results on 22nm FDSOI MOSFETS (Leti, NXP) VT mismatch (@ 1V Vd) for FDSOI nFETs and pFETs. High-k/metal gate stack. STI isolation. TSi=6nm, Lmin=30nm, Wmin=80nm VT mismatch for UT2B vs thick BOX MOSFETs. High-k/metal gate stack. STI isolation. TSi=8nm. • Record matching performance for FDSOI (top) • VT matching not degraded by UTBOX vs Thick box substrates (bottom) MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 22, 2010 28 28

  29. Task T2.3 D2.3.1: Parametric mismatch fluctuation effects in 32 nm SOI FinFETs (NXP, LETI) GIDL VT Rseries Mismatch signature analysis on FinFET population. WFin=10 nm, Lg=100 nm a: collection of 96 (VDS=1.2 V) transfer curves for transistor 1 (ID1) of each pair. b: ΔID/ID vs. VGS for all pairs of the population (ΔID/ID = 200 x (ID1-ID2)/(ID1+ID2) ). c: mismatch signature: σ_ΔID/ID (red triangles) and mismatch auto-correlation (black X’s) vs. VGS. a: Drain access resistance improvement from 700 to 280 Ωμm . θ vs. β slope corresponds to RSD. b: VT mismatch fluctuations vs. area. AΔVT increases from 1.9 mVμm (solid line) to 2.4 mVμm (dashed line) with 1018 channel doping • Powerful Mismatch signature analysis concept demonstrated • AΔVT down to 2 mVμm range demonstrated MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 30, 2010 MODERN 1st Year Review June 22, 2010 29 29

  30. T2.3 action items • Task 2.3: Characterization and simulation verification • D2.3.2 (M18)/D2.3.4 (M36): « 1/f noise dispersion” => AI (WP leader): Ask NXP about plan to develop compact model within Modern • D2.3.4: (M36) «  Report on high-level models, both analytical and graphical , for PV of in Non-Volatile-Memory devices (NMX)” • AI change title: «  Report on high-level models, both analytical and graphical , for PV of devices in Non-Volatile-Memory technologies (NMX)” Project Review Meeting Catania, Nov 09-10, 2010

  31. MODERN General MeetingTask 2.4 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010

  32. Reliability: T2.4 Deliverables Task Leader: Jong-mun.park@austriamicrosystems.com  32 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  33. WP2/ Task 2.4 contributions AI(all, end 2010): WP2 and per Task work matrix completion 33 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  34. T2.4 Review Summary Activity done so far, with highlights on technical results, and dissemination - D2.4.1 deliverable: done. - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations. - Initial physics-based analytical model for NBTI to implement in circuit simulator. - Time dependent modeling of degradation for NBTI & HC. Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS. - Hot-Carrier lifetime model for HV-CMOS by modified Hu-model. - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node. Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. - Analytical NBTI and HC model developments for LV- & HV-CMOS. 34 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  35. NBTI & Hot-Carrier Activities (1) 35 • Extraction of capture/emission time maps • Compact modeling using RC circuits MODERN General Meetings Catania, Nov. 9 & 10, 2010

  36. NBTI & Hot-Carrier Activities(2) • SE-mechanism: • ME-mechanism: • Idlin degradation represented by the compact model 36 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  37. Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node 37 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  38. Modified Model of Hu: blue data points: -40°C red data points: +25°C Vd: 35V, 40V, 45V, 50V, 55V Lifetime Models for High-Voltage NMOS 38 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  39. WP2 action items • Task 2.4: Statistical Reliability • D2.4.2 (M24): « Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)” => AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects • D2.4.3 (M33) « Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)” • AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices remains challenging task (physics complexity); nevertheless achievable with some approximations to physics • AI (UNGL): UNGL to clarify contents of contribution to NBTI/HCI compact models Project Review Meeting Catania, Nov 09-10, 2010

  40. MODERN General MeetingTask 2.5 summary Catania, Nov. 9-10 2010 Project Review Meeting Catania, Nov. 9-10, 2010

  41. Compact Modeling: T2.5 Deliverables Task Leader: paolo.pavan@unimore.it Project Review Meeting Catania, Nov. 9-10, 2010 18/09/2014 41

  42. Variations in statistical models: sources Local Systematic (Layout dependent) Local Statistical Global Process Line edge roughness Die to die Poly Si granularity Wafer to wafer H.Tsuno, Sony, VLSI 2007 Channel dopants Across chip Source: A.Asenov

  43. UNGL Deliverable 2.5.1 NMOS IDVD Capacitance fit atVD=0V NMOS with substrate bias Capacitance fit atVD=1.1V Extraction of accurate uniform compact models, DC and AC MODERN General Meetings Catania, Nov. 9 & 10, 2010 43

  44. UNGL Deliverable 2.5.1 NMOS and PMOS parametercorrelations Distribution of fitted error for different parameter sets Selection of optimal statistical parameter set and statistical compact model extraction Preservation of parameter correlations MODERN General Meetings Catania, Nov. 9 & 10, 2010 44

  45. Statistical Models for Circuit Simulation Spice model Layout Proximity / Middle end Parasitics Variations: Global Local Corners construction Nominal Design inputs Core Compact model Circuit environment VDD, T, … Statistical models: MC, Corners Design Analysis Settings for Variations: Corners/ MC/ DOEs Distributions Corners Yield Elementary Circuit Responses Complete simulation file Simulation engine Netlist extracted from Layout

  46. T2.5 action items • Task 2.5: compact modeling • D2.5.2 (M30):  » Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)” • AI (STF2, Dec 2010): To clarify if D2.5.3 contribution (45nm Analog) effectivelytransformsinto D2.5.2 contribution (32nm Digital) • D2.5.3 (M33): « PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)” => AI(WP leader, same as AI as D2.2.5, Nov 2010): to contact LETI, cc UNGL on demonstratordevices (FDSOI, Finfets?,…) and associatedtemplates. Backup templatedevicesalreadyavailableat UNGL. NeeddecisionlatestFeb 2011. Project Review Meeting Catania, Nov 09-10, 2010

  47. Contents • WP2 introduction • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting Project Review Meeting Catania, Nov 09-10, 2010

  48. WP2 meetingDomain overview per task and partner • PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). • Significant communalities of technology targets, except different ones for Process and Device simulation. • (not funded) MODERN General Meetings Catania, Nov. 9 & 10, 2010

  49. WP2/ Task 2.4 contributions AI(all, end 2010): WP2 and per Task work matrix completion 49 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  50. WP2 meeting: Gantt chart AI(all): requires completion (links with other WPs), and review by email within 2 months Project Review Meeting Catania, Nov 09-10, 2010

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