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LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS

This project aims to reduce power consumption by operating a 32-bit adder at reduced voltage, coupled with level converters. The effect of voltage reduction on power consumption and delay of the adder will be studied, as well as the characterization of the level converters.

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LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS

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  1. LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department Auburn University ELEC 6270-001 Class Project Presentation

  2. Objectives • To reduce the power consumption by operating the adder at reduced voltage, coupled with level converters. • To study the effect of Voltage reduction on the Power consumption and delay of the adder • To characterize the Level Converters for power consumption and delay ELEC 6270-001 Low-Power Design of Electronic Circuits

  3. Setup for Low Voltage Operation VDD_L Low Voltage outputs High Voltage inputs Low-to-High Level Converter High Voltage Outputs 33 32-bit Adder 33 65 ELEC 6270-001 Low-Power Design of Electronic Circuits

  4. Why Level Converters??? (2) (1) VDD_L ( = 2.5 V) VDD_H ( = 3.3 V) Vout_L Vout_H ( ‘0’= 0 V) (‘1’= 2.5V) ( ‘0’= ???) (‘1’= 3.3V) Vin_H Vin_L ( ‘0’= 0 V) (‘1’= 3.3V) ( ‘0’= 0 V) (‘1’= 2.5V) So……… only a Low-to-High Level Converter is required!! ELEC 6270-001 Low-Power Design of Electronic Circuits

  5. Low-to-High Level Converter Transistors with thicker oxide and longer channels VDD_H p1 p2 Vout_H Vin_L n2 n1 VDD_L N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Section 12.4.3, Addison-Wesley, 2005. ELEC 6270-001 Low-Power Design of Electronic Circuits

  6. Adder and Level Converter Design • The 32-bit adder was designed using VHDL • Synthesized with 0.35 micron TSMC technology using Leonardo - Area = 224 gates • Designed the Level Converters using Design Architect • Timing and Power analysis was done using ELDO ELEC 6270-001 Low-Power Design of Electronic Circuits

  7. Normal (High) Voltage Operation of the Adder • VDD = 3.3 V • Power Dissipation = 2.1120 miliwatt • Delay = 0.55882 ns ELEC 6270-001 Low-Power Design of Electronic Circuits

  8. Experimental Results * The power consumption values when the level converter fails ELEC 6270-001 Low-Power Design of Electronic Circuits

  9. Delay Break-Up ELEC 6270-001 Low-Power Design of Electronic Circuits

  10. Power Versus Voltage Plot for the Adder P α VDD2 ELEC 6270-001 Low-Power Design of Electronic Circuits

  11. Delay versus Voltage Plot for the Adder = 1.5 ELEC 6270-001 Low-Power Design of Electronic Circuits

  12. Power-Delay Product Plot for the Adder VDD = 1.5V P = 0.359 mW D = 1.59 ns ELEC 6270-001 Low-Power Design of Electronic Circuits

  13. Reason for High Power Consumption in Level Converter VDD_H p1 p2 Vout_H Vin_L n2 n1 VDD_L The p1 – n1 and p2 – n2 transistors stay ON simultaneously for time >= the inverter delay, thus substantial short circuit power dissipation. ELEC 6270-001 Low-Power Design of Electronic Circuits

  14. VDD_H CK Vin_L CK Alternative Design of a Level Converter Dynamic CMOS Inverter p Vout_H n1 Inverter Operating at the regular supply voltage (VDD_H) n2 High Voltage clock ELEC 6270-001 Low-Power Design of Electronic Circuits

  15. Low Voltage Adder Operation with the Dynamic CMOS based Low-to-High Level Converter ~ 5% reduction in power consumption ELEC 6270-001 Low-Power Design of Electronic Circuits

  16. Problem with this design too!!  Dynamic CMOS based Level Converter Conventional Level Converter Gives rise to glitches due to the precharge phase of the clock ELEC 6270-001 Low-Power Design of Electronic Circuits

  17. Conclusion • The power consumption of the conventional level converter is too high to be used with the adder for power reduction. Need a one with lesser power consumption. • The optimum voltage for a low-voltage operation of the adder was found to be ~ 1.5 V, at which Power consumption = 0.36 mW (a drop of 83% from 2.112 mW at 3.3V ) Delay = 1.594 ns (three times increase from 0.56 ns at 3.3V) ELEC 6270-001 Low-Power Design of Electronic Circuits

  18. Future Work • Investigate the effectiveness of using a level converter based flip flop [1],[2], in order to incorporate the level conversion in the register following the combinational logic. • Use of other low power level converters [1]. ELEC 6270-001 Low-Power Design of Electronic Circuits

  19. References • Class Lectures • N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition • ELDO User Manual • [1] F. Ishihara, F. Sheikh, B. Nikolic, “Level Conversion for Dual-Supply Systems,” in IEEE Transactions on VLSI Systems, Vol. 12, No. 2, Feb. 2004, pp.185–195. • [2] F. Klass, “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic,” in Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 108 – 109. ELEC 6270-001 Low-Power Design of Electronic Circuits

  20. THANK YOU!!! ELEC 6270-001 Low-Power Design of Electronic Circuits

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