Design of a 32-Bit Hybrid Prefix-Carry Look-Ahead Adder By

1. Design of a 32-Bit Hybrid Prefix-Carry Look-Ahead Adder By Sulabh Vidyarthi

2. HYBRID PREFIX-CLA • GOAL: • To Implement a 32-bit hybrid prefix-carry-look-ahead adder. • Implementation style to be used,static and dynamic. • Test the design for Power and speed.

3. BACKGROUND • Parallel Prefix Adders(PPA): • Carry operator “O” on (g,p) signal pairs where, g=g”+p”g’ p=p’p” Operator “O” is associative => [(g”’,P”’) O(g”,p”)]O(g’,p’)=(g”’,p”’)O[(g”,p”)O(g’,p’)] g’,p’ g”,p” “O” g,p

4. Parallel Prefix Adder(cont) • Given (p,g) terms for each bit ,they can be grouped together to find “all” the prefixes ,which is equivalent to computing all the carries in parallel. • Since operator “O” is commutative (g,p)’s can be grouped in any order. • However ,note that “O” is not commutative .

5. Conventional Prefix Adder(Brent-kung Adder)

6. Analysis Of PPA’s • Following highlight the characteristics of a general PPA: • Number of “O” cells • Tree cell height(delay) • Tree cell Area • Cell fan-in and fan-out • Wiring congestion or wiring length • Delay path variation(glitching)

7. Hybrid Prefix Carry Look-Ahead • Use of 4-bit Carry-look-ahead blocks to group g’s and p’s. • Reduces the fan-in and fan-out of any operator “o” block to 2,which in turn reduces input capacitance and as a result faster carry propagation path. • The wiring overhead is greatly reduced,which is very important at deep sub-micron levels as it reduces wiring capacitance and thus low power dissipation. • Balanced Delay path (don’t want glitching).

8. HYBRID PREFIX-CLA(cont)

9. Analysis of Design • L1: g,p generation using inputs A and B • L2:Grouping of g and p to generate group carry G and P( G0 G4---G28,P0 P4---P28) • L3:Using Operator “O” on the group G and P to generate Gr4 and Pr4 eg:Gr4=G4+P4.G0,Pr4=P0P4 • L4: Carry generator.eg C4=Gr4+Pr4.C0 • L5:Sum generation using 4-bit carry look-ahead generator

10. Analysis(cont) Delay Analysis: • L1(1T) + L2(3T) + L3(2T) + L4(2T)+L5(2T)=10T • The critical path is through L1-L4 + One CLA Adder unit in L5. • T=one gate delay

11. Tool Flow • Gate level design of the static and dynamic adders :verilog(Modelsim) • Extraction to transistor level (Synopsys and Cadence) • Delay and power analysis :Cadence

12. Result Worst case delay and power estimate

13. Conclusion • Static and dynamic design both are faster than the normal look-ahead adders. • Easy implementation and simple design using only AND,OR and XOR gates . • Static design has obvious power advantages over the dynamic design.The high power dissipation of dynamic design outweighs its advantages of high speed. • The Hybrid Prefix CLA has definite speed advantage over several other adders.Reduction in power dissipation in Domino and Dual rail Domino is a potential research area.Techniques such as using Mixed-Swing Dual Rail Domino topology* can give Hybrid Prefix adders and edge over other adder types both in terms of speed and Power. *Mixed-Swing Quad- Rail for Low Power Dual-Rail Domino Logic(Bharath Ramasubramanian,L. Richard,Herman Schmit)

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