COMP211 Computer Logic Design Lecture 5. Hardware Description Language #1

1. COMP211Computer Logic DesignLecture 5. Hardware Description Language #1 Prof. Taeweon Suh Computer Science Education Korea University

2. Topics We are going to discuss the following topics in roughly 3 weeks from today • Introduction to HDL • Combinational Logic Design with HDL • Sequential Logic Design with HDL • Finite State Machines Design with HDL • Testbenches

3. Introduction • Example: • Number of transistors in Core 2 Duo: ~300 million • Assuming that the gate count is based on 2-input NAND gate, (which is composed of 4 transistors), do you want to draw 75 million gates by hand? Absolutely NOT! In old days (~ early 1990s), hardware engineers used to draw schematic of the digital design, based on Boolean equations, FSM, and so on… But, it is not virtually possible to draw schematic as the hardware complexity increases

4. Introduction • Another Example: • Even a simple FSM design problem in the midterm exam took you more than 30 minutes • Even worse, many of you got your answer wrong in the exam! As the hardware complexity increases, there has been a necessity of designing hardware in a more efficient way

5. Introduction CAD Tool Optimized Gates HDL-based Design module example( input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Hardware description language (HDL) • Allows designer to specify logic function using language • So, hardware designer only needs to specify the target functionality (such as Boolean equations and FSM) with language • Then a computer-aided design (CAD) tool produces the optimized digital circuit with gates • Nowadays, most commercial designs are built using HDLs

6. Introduction IEEE: Institute of Electrical and Electronics Engineers s a professional society responsible for many computing standards including WiFi (802.11), Ethernet (802.3) etc Two leading HDLs: • Verilog-HDL • Developed in 1984 by Gateway Design Automation • Became an IEEE standard (1364) in 1995 • We are going to use Verilog-HDL in this class • The book below is a good reference, but not required to purchase the book below • VHDL • Developed in 1981 by the Department of Defense • Became an IEEE standard (1076) in 1987

7. HDL to Gates There are roughly 3 steps to design hardware with HDL • Hardware design with HDL • When describing circuits using an HDL, it’s critical to think of the hardware the code should produce. • Simulation: Once you design your hardware with HDL, you need to verify if the design is implemented correctly • Input values are applied to your design with HDL • Outputs checked for correctness • Millions of dollars saved by debugging in simulation instead of hardware • Synthesis • Transforms HDL code into a netlist, describing the hardware • Netlist is a a text file describing a list of gates and the wires connecting them

8. CAD tools for Simulation There are renowned CAD companies that provide HDL simulators • Synopsys • www.synopsys.com • Cadence • www.cadence.com • Mentor Graphics • www.mentorgraphics.com • We are going to use ModelSim Xilinx Edition-III (MXE-III) for simulation • http://www.xilinx.com/ise/optional_prod/mxe.htm • Install the tool on your PC

9. CAD tools for Synthesis Xilinx ISE The same companies (Synopsys, Cadence, and Mentor Graphics) provide synthesis tools, too • They are extremely expensive to purchase though So, in this class, we are going to use a free synthesis tool (Xilinx ISE WebPACK) from Xilinx • http://www.xilinx.com/ise/logic_design_prod/webpack.htm • Install the tool on your PC

10. Verilog Modules Module • A block of hardware with inputs and outputs • Examples: AND gate, multiplexer, priority encoder etc Two general styles of describing module functionality • Behavioral modeling • Describe the module’s functionality behaviorally (?) • Structural modeling • Describe the module’s functionality from combination of simpler modules

11. Verilog Modules module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule A Verilog module begins with the module name and a listing of the inputs and outputs Assign statement describes combinational logic “~” indicates NOT “&” indicates AND “|” indicates OR

12. Behavioral Modeling Example module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Behavioral modeling • Describe the module’s functionality behaviorally

13. Structural Modeling Example // Behavioral model module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule module example_structure(input a, b, c, output y); wire inv_a, inv_b, inv_c; wire and3_0, and3_1, and3_2; inv inva (a, inv_a); inv invb (b, inv_b); inv invc (c, inv_c); and3 and3_y0 (inv_a, inv_b, inv_c, and3_0); and3 and3_y1 (a, inv_b, inv_c, and3_1); and3 and3_y2 (a, inv_b, c, and3_2); or3 or3_y (and3_0, and3_1, and3_2, y); endmodule module inv(input a, output y); assign y = ~a ; endmodule module and3(input a, b, c, output y); assign y = a & b & c; endmodule module or3(input a, b, c, output y); assign y = a | b | c; endmodule Structural modeling • Describe the module’s functionality from combination of simpler modules

14. Simulation module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule

15. Synthesis module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Synthesis • Transforms HDL code into a netlist, that is, collection of gates and their connections