Sequential Equivalence Checking for Clock-Gated Circuits

1. Sequential Equivalence Checking for Clock-Gated Circuits Hamid Savoj Robert Brayton Niklas Een Alan Mishchenko Department of EECS University of California, Berkeley

2. Overview • Motivation • Notation • Theorems • Asymmetry • Implementation • Experiments • Conclusions

3. Clock Gating Two circuits, A and B, should be verified equivalent when an enabling signal E has been used for clock gating in B

4. Motivation • Useful sequential circuit transformations include • Clock gating, loop removal, redundancy removal • However, sequential equivalence checking (SEC) remains a hard computational problem • A better SEC methodology is required • We develop a SEC methodology, which • Works for some useful sequential transforms • Reduces SEC to CEC, which has lower complexity • SEC is PSPACE-complete; CEC is NP-hard

5. A A A A Notation • A is a sequential circuit • Andenotes the combinational circuit derived as shown below where • A is unrolled n times • outputs of Anare the n POs from each frame plus the FF inputs at the end of the nth frame • inputs are n PIs plus initial FF outputs PO PO PO PO FF Outputs FF Inputs PI PI PI PI

6. A A A A B B B Notation • A and B are two sequential circuits with • the same inputs and • the same number of FFs • [ An,Bk ] is the combinational circuit connected through their FFs inputs/outputs [ A4,B3] PI PO FF inputs FF outputs FF outputs

7. Notation • If C and D are combinational circuits, C = D denotes that they are combinationally equivalent • If AandB are sequential circuits, denotes that AandB are sequentially equivalent

8. Observability Theorem Theorem 1: If there exists a 1-1 mapping between the FFs of A and B, such that , then for any initial state. i.e. A and B are sequentially equivalent

9. If all outputs are , then Reducing SEC to CEC PI1 PI2 PI3 Why do we need a 1-1 mapping?

10. Proof: (see picture) Proof of Theorem 1 • Statement: • POs of Frame 1 are equal • POs of Frame 2 are equal • Flops of Frame 2 are equal

11. Controlability Theorem Theorem 2: If there exists a 1-1 mapping between the FFs of A and B, such that , then for any initial state that can be reached by A after n cycles.

12. Controlability/Observability Theorem Theorem 3: on the subset of states that can be reached by A after one cycle.

13. A A A = = = = A B A = = = = = = = = = A-controllable, A-observable? (justify – propagate) How about combined observability/controllability? A A A A A A B A A A B B Theorem 1 (A-observability) Theorem 2 (A-controllability) A A B A B B Theorem 3 (A-controllable, B-observable)

14. A A A = A B A = = Counter-example

15. R R R R S S S S D D D D Q Q Q Q Verification Asymmetry: AA = BA F2(1) e(0) F1(1) e(1) e A AA a(1) F1 a(0) F2(2) 0 F2(1) 0 b(1) b(0) 1 1 a Q F1(1) F1(0) 0 F2(0) b 0 0 1 0 1 F2 c 1 1 Q(2) Q(1) c(1) c(0) e F2(1) e(0) F1(1) e(1) B BA F1 a(1) a(0) F2(2) 0 F2(1) 0 b(1) F2(0) a 1 1 Q 0 0 F1(1) F1(0) b 1 F2(0) 1 F2 0 0 v 1 1 Q(2) Q(1) c(1) c(0)

16. R R R R S S S S D D D D Q Q Q Q Verification Asymmetry: AB != BB F2(1) e(0) F1(1) e(1) AB e A a(1) a(0) F2(2) 0 F2(1) F1 0 b(0) 1 1 a F1(1) F1(0) F2(0) Q 0 b 0 0 0 1 1 1 1 F2 Q(2) Q(1) c c(1) c(0) e F2(1) e(0) F1(1) e(1) B BB F1 a(1) a(0) F2(2) 0 F2(1) 0 a F2(0) 1 Q 1 0 0 b 1 F1(1) F1(0) F2(0) 1 F2 0 0 v 1 1 Q(2) Q(1) c(1) c(0)

17. Improvements in CEC • Resulting CEC problems have deep logic and are hard • Typically CEC is solved by SAT sweeping (detecting and proving internal candidate equivalences); in this case, there are many candidates and many of them are hard to prove • Developed a general CEC procedure, which skips some intermediate equivalences • The result for the relevant CEC problems was • 5x reduction in runtime • solved previously unsolved problems • Given a combinational miter with equivalence class {A, B, A’, B’} • try to prove A=A’ and B=B’ • do not try to prove A = B, A = B’, etc A’ A B’ B D1 D2

18. Implementation • The proposed algorithm is implemented as command absec in ABC • The command takes two networks and the number of timeframes to unfold

19. Experimental Results • Six industrial benchmarks were transformed using sequential clock-gating transforms, based on intuitively correct sequential ODC arguments

20. Experimental Results • K is the number of timeframes • New is proposed implementation (absec) • General is general SEC (dsec) • Runtime is in minutes on Intel(R) Xeon(R) CPU X5570 @ 2.93GHz

21. Conclusions • We introduced several scenarios when SEC can be replaced by CEC with considerable reduction of computational effort • The methods are conservative; if the checks fail, nothing is implied about non-equivalence • Some conditions when the checks are expected to succeed, include sequential clock-gating and redundancy removal • Future work focuses on sequential synthesis that is provably verifiable using the proposed method

22. Abstract • Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general-case for sequential equivalence checking (SEC). This talk discusses conditions when SEC can be reduced to combinational equivalence checking (CEC). These can be applied to many sequential clock gating transforms, where correctness is argued intuitively using a finite unrolling of a sequential design. A method based on these theorems was applied to six large industrial examples. It completed on all examples and was about 30x faster on the three examples where the conventional engine was able to finish.