Extreme Makeover for EDA Industry

1. Extreme Makeoverfor EDA Industry Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine www.cecs.uci.edu/~gajski

2. Past, Present and Future

3. Simulation based methodology Simuletable but not synthesizable or verifiable

4. Arithmetic Algebra < objects, operations> Arithmetic algebra allows creation of expressions and equations

5. Model Algebra <objects, compositions> Model algebra allows creation of models and model equivalences

6. Specify-Explore-Refine Methodology Design decisions Model refinement Replacement or re-composition

7. Refinement Each designer decision Several transformations Model refinement

8. Verification Transformations New model Verify equivalence

9. Synthesis Estimate metric Evaluate options Design decision

10. Simulation

11. System Design Environment

12. Y-Chart

13. Finite-State-Machine with Data (Processor-level behavioral model: FSM +DFG)

14. IR SR Processor Architecture (Processor-level structural model: RTL components) Data memory Control inputs Control signals Selector Register Cache RF Bus1 Bus2 Next- state logic or Address generator State register or PC Output logic or Program memory    ALU Latch Bus3 Signal status Register Datapath Controller Control outputs Datapath outputs

15. Processor Semantics Objects: - RTL Components • Alus • Multipliers • Registers • RF - Connections • Buses • Wires Composition: - Netlist • Objects: • - States • Transitions • Statements • Composition: • - Statements • • Sequential • • Parallel • - Transitions • • Conditional • • Unconditional Processor

16. Data memory Control inputs Control signals Op1 Op2 RF Op1 Op2 Op3 IR Selector D Q S1 S2 Register Memory D Q Op4 Bus1 Op1 Op2 Next- state logic or Address generator S3 Bus2 D Q Op5 Op6 Output logic or Program memory State register or PC ALU    Op3 Latch Bus3 SR Signal status Register Controller Datapath RTL Processor Control outputs Datapath outputs Processor Synthesis Variable binding Operation Binding Rescheduling Bus Binding Allocation FSM Synthesis Processor FSMD model

17. Program-State Machine (System-level behavioral model: UML + C)

18. System Architecture (System-level structural model: system components)

19. System System (Transaction-Level) Semantics Objects: - Behaviors - Channels Composition: - Hierarchy - Order • Sequential • Parallel • Piped • States - Transitions • TI • TOC, TOS, ... - Synchronization Objects: - Components • Proc • IP • Memories • IF - Connections • Buses • Wires Composition: (same as in Behavior Model) Objects: - Behaviors - Channels Composition: - Hierarchy - Order • Sequential • Parallel • Piped • States - Transitions • TI • TOC, TOS, ... - Synchronization

20. µProcessor IP Memory Comp. Proc Proc Proc Interface Interface Proc Proc Bus Interface Interface Memory Custom HW System architecture PSM model System Synthesis Scheduling Behavior Binding Channel Binding Allocation IF Synthesis Profiling Refinement System

21. SCE2 Decision User Interface (DUI) Validation User Interface (VUI) Capture Profiling Specification model Profiling data Sys. Comp IPs Arch. synthesis Design decisions Arch. refinement Select Partition Compile Estimation Architecture model Map Check Estimation results Schedule Simulate Buses Protocols Comm. synthesis Insert Verify Design decisions Comm. refinement Assemble Estimation Communication model Estimation results RTL Comp. RTOS CA synthesis Design decisions CA refinement Estimation results Estimation Implementation model Comm. Libraries Commercial Tools

22. Refinement Effort Modified lines Manual Automated User / Refine SpecArch 3,275 3~4 mons. 15 mins / <1 min ArchComm 914 1~2 mons. 5 mins/ <0.5 min CommImpl 6,146 5~6 mons 30 mins / <2 mins Total 10,355 9~12 mons 50 mins / <4 mins Some Results • Experiment on GSM Vocoder design (10K lines of code) • Conclusion • Productivity gain >2,000X for industrial strength designs • Compare 9-12 months (manual refinement) vs. 50+4 minutes (user decisions + automatic refinement) • Enables extensive design exploration (60/day) Source: J. Peng, PHD Thesis

23. Refinement Effort Modified lines Manual Automated User / Refine SpecArch 751 1~2 mons. 5 mins / <0.5 min ArchComm 492 ~1 mons. 3 mins/ <0.5 min CommImpl 1,278 3~4 mons 20 mins / <1 mins Total 2,521 5~7 mons 28 mins <2mins Some Results • Simulation Speed & Code size • Refinement Effort • Compare 5-7months (manual refinement) vs. 28 minutes (user decisions) + 2 minutes (automatic refinement) Source: J. Peng, PHD Thesis

24. Conclusions • Extreme makeover is necessary for a new paradigm, where • SW = HW = SOC = Embedded Systems • Simulation based chaos is not acceptable • Design methodology is based on scientific principles • Model algebra is enabling technology for • System design • System modeling and simulation • System verification • System synthesis • Formalism introduces simplicity that allows • Automatic model generation (No need for languages) • Exploration and synthesis (Simplifies design algorithms) • Equivalence verification (Guarantees equivalence)