Reconfigurable Computing (EN2911X) Lecture 01: Introduction

1. Reconfigurable Computing (EN2911X) Lecture 01: Introduction Prof. Sherief Reda Division of Engineering, Brown University Spring 2007

2. Methods for executing algorithms Reconfigurable computing Software-programmed processors Hardware (Application Specific Integrated Circuits) • Advantages: • very high performance and efficient • Disadvantages: • not flexible (can’t be altered after fabrication) • expensive • Advantages: • fills the gap between hardware and software • much higher performance than software • higher level of flexibility than hardware • Advantages: • software is very flexible to change • Disadvantages: • performance can suffer if clock is not fast • fixed instruction set by hardware

3. Temporal vs. spatial based computing Temporal-based execution (software) Spatial-based execution (reconfigurable computing) • Ability to extract parallelism (or concurrency) from algorithm descriptions is the key to acceleration using reconfigurable computing

4. Reconfigurable devices • Field-Programmable Gate Arrays (FGPAs) are one example of reconfigurable devices • An FPGA consists of an array of programmable logic blocks whose functionality is determined by programmable configuration bits • The logic blocks are connected by a set of routing resources that are also programmable • Custom logic circuits can be mapped to the reconfigurable fabric

5. Configuring FPGAs [Maxfield’04] • FPGAs can be dynamically reprogrammed before runtime or during runtime (virtual hardware) • full • partial

6. Uses of reconfigurable devices • Low/med volume IC production • Early prototyping and logic emulation • Accelerating algorithms in reconfigurable computing environments • Reconfigurable functional units within a host processor (custom instructions) • Reconfigurable units used as coprocessors • Reconfigurable units that are accessed through external I/O or a network [Compton’02]

7. Current problems with conventional computing Intel VP Patrick Gelsinger (ISSCC 2001) “If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.” • Technology scaling doubled the number of devices in an IC (processors, FPGAs, …, etc) every 2-3 years • Scaling also provided devices with reduced delay → frequency doubling (with aggressive pipelining) → increased power density • Increases in clock frequency slowed down (or stopped); available devices are used to create multi-processor (multi-core) processors

8. Why reconfigurable computing is more relevant these days? • Demand for high-performance computation is soaring: • large-scale optimization problems, physics and earth simulation, bioinformatics, signal processing (e.g. HDTV), …, etc) • Why software-programmed processors are no longer attractive? • Faster temporal execution of instructions) is no longer improving • General-purpose multi-core processors requires coarse grain thread-level parallelism • Why reconfigurable fabrics are currently attractive? • Increased integration densities allow large FPGAs that can implement substantial functions • Provide the spatial computational resources required to implement massively-parallel computations directly in hardware

9. Topics that will be covered in this class… (entry survey time)

10. Topic 01: Programmable logic technology overview Programming information could be stored in SRAM 4-input Look-Up Table (LUT) is the typical size

11. Topic 01: Programmable logic technology overview Switch box

12. Topic 02: Reconfigurable computing methodologies compile for target processor software System Specification partitioning hardware synthesis (compilation) Mapping (placement & routing) configuration data

13. Topic 03: Hardware programming languages (Verilog) • Verilog is a hardware description language used to model digital systems • Similar in syntax to C • Differs from conventional programming languages as the execution of statements is not strictly linear. Possible to have sequential and concurrent execution statements • The language can be synthesized into logic circuits module mux(a, b, select, y); input a, b, select; output y; initial begin always @ (a or b or select)    if (select)       y = a; else       y = b; end endmodule

14. Topic 04: Rapid prototyping with Altera DE2 board • No need to design our board; we will use Altera’s DE2 board and Quartus II software. • Features: • Cyclone II FPGA 35K LUTs • 10/100 Ethernet • RS232 • Video out (VGA 10-bit DAC) • Video in (NTSC/PAL/multi-format) • USB 2.0 (type A and type B) • PS/2 mouse or keyboard port • Line in/out, microphone in (24-bit Audio CODEC) • Expansion headers (76 signal pins) • Infrared port • Memory 8-MBytes SDRAM, 512K SRAM, 4-MBytes flash • SD memory card slot • Displays 16 x 2 LCD display • Eight 7-segment displays • Switches and LEDs

15. Topic 05: High-level synthesis languages (SystemC) #include "systemc.h" SC_MODULE(adder) { sc_in<int> a, b; sc_out<int> sum; void do_add() { sum = a + b; } SC_CTOR(adder) { SC_METHOD(do_add); sensitive << a << b; } }; • SystemC is a system description language for hardware/software systems • SystemC is a set of library and macros implemented in C++ to allow specification and simulation of concurrent processes • Allow high-level description of hardware modules • A subset of the language can be synthesized into logic circuits. We will use Celoxica Agility compiler as our synthesizer tool

16. Topic 06: Algorithm acceleration using reconfigurable computing • Learn how to use FPGAs and reconfigurable computing principles to accelerate algorithms: sorting, dynamic programming, NP-hard problems, …, etc. • Accelerating application in various fields • Signal and image processing • Cryptology • Bioinformatics • Pattern recognition … etc

17. Topic 07: Soft multi-core computing environments Nios processor Core 1 Nios processor Core 2 • Learn about hard and soft processors • Design multi-core-based reconfigurable computing systems • Design of on-chip networks for multi-core systems • Design of custom instructions • Design of pluggable acceleration function units BUS Accelerator Memory

18. Goals of this class • Learn principles of reconfigurable computing with minimum hardware bakground • Acquire hands-on experience and useful implementation skills • Verilog / SystemC / Quartus II • Develop/strengthen research skills

19. Class organization • HW assignments (paper reviews + mini labs): 20% • Class participation: 10% • Midterm: 20% • Class project (progress/final reports and presentation): 50% • Sources: papers, lecture slides, manuals and book chapters. • Class website: http://ic.engin.brown.edu/classes/EN2911F07