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DSP handling of Video sources and Etherenet data flow. Technion – Israel Institute of Technology High speed Digital Lab. Supervisor : Moni Orbach Students : Reuven Yogev Raviv Zehurai. Project Objective.
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DSP handling of Video sources and Etherenet data flow Technion – Israel Institute of Technology High speed Digital Lab Supervisor: Moni Orbach Students: Reuven Yogev Raviv Zehurai
Project Objective Uniting 4 video sources by DSP to a combined image and transferring the data through Ethernet.
Evaluation Board Memories 00100 FIFO Bridging Card DSP 00100 10100 00011 Video Sources 00100 Ethernet Controller System Structure
Clock FPGA EPC2 Video Source Connector Evaluation Board Connector Bridging Card
Some Figures • M4088 Video Sources - based on OV5017 CMOS image sensor (4 MB/sec.) • FPGA (On the bridging Card) • DSP Evaluation Board (Ateme) • TI DSP 6416 (100 MB/sec.) • Ethernet Controller Card • FIFO (coordinates the different rates) • Memories (~10 MB)
Time tables • Hardware Design – Completed • Hardware Implementation – Completed • Integration – In process • Software Design – In process Estimated due date : August 2004