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Buddy Walk-in @ Chennai on October 23, 2010 (Saturday). Requirements: 1. ASIC Implementation (Synthesis, STA, Formal verification) - Experience on high speed synthesis (1GHz) using DC, Timing Analysis experience using Primetime, Formal Verification using Cadence LEC
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Buddy Walk-in @ Chennai on October 23, 2010 (Saturday) Requirements: 1. ASIC Implementation (Synthesis, STA, Formal verification) - Experience on high speed synthesis (1GHz) using DC, Timing Analysis experience using Primetime, Formal Verification using Cadence LEC 2. ASIC Gate Level Simulation – Experience in Gate level simulation of multi-million ASICs 3. ASIC Design Lead – Experience in Micro-architecture, RTL coding, Hands-on ASIC Synthesis/STA, Supporting physical design team on timing closure, Floorplan and Powerplan 4. Modeling – Experience in Modeling using SystemC 5. ASIC Verification – Experience in verifying ARM based ASICs, Strong in Testbench architecture, Testplan extraction, SystemVerilog/Specman/Vera experience along with OVM or VMM methodology 6. DFT Lead – In-depth knowledge of DC/AC tests and on-chip compression techniques, Strong pattern simulation and failure debugging experience with/without SDF, Must have Synopsys DFT tools experience Timings: 9:30 a.m -2:30 p.m Venue Details: L & T InfoTech, Chennai TC3, L& T InfoTech Park, Mount Poonamallie Road, Manapakkam-Chennai Contact Person: Ms. Nethra Nagaraj T: 91- 044 2253 5772 Please ask your buddies to carry latest resume and last 3 months pay-slip. Experience: 3 – 8 years Education: BE/ BTech/ MTech/MS/ME Location: Chennai & Bangalore Reward: As per the Buddy Scheme Note: In case your buddy is not able to attend the walk-in interview, please send his /her resume to: Nethra.nagaraj@lntinfotech.com