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Exemple d’exécution d’un programme

Traduction en hexa. Jeux d’instructions de la machine. ISTORE 1. 0x36 0x01. Exemple d’exécution d’un programme. Exemple chargement d’une instruction. Memory control signals (rd,wr,fetch). 3. 4 to 16 Decoder. 4. MPC. 9. 0x00. 8. 0x36. 8. 0x05. 0x00. JMPC. MIR. C. Addr. J. M.

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Exemple d’exécution d’un programme

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  1. Traduction en hexa Jeux d’instructions de la machine ISTORE 1 0x36 0x01 Exemple d’exécution d’un programme

  2. Exemple chargement d’une instruction Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 4 MPC 9 0x00 8 0x36 8 0x05 0x00 JMPC MIR C Addr J M Alu B 0x04 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  3. Exemple Istore (H=LV; Goto Istore2) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 4 MPC 9 0x01 8 0x36 8 0x05 0x00 JMPC MIR C Addr J M Alu B 0x04 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  4. Exemple Istore (MAR=MBRU+H; Goto Istore3) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 4 MPC 9 0x01 8 0x01 8 0x05 0x00 JMPC MIR C Addr J M Alu B Arrivée de la donnée.(Lecture déclenchée dans le Main1) 0x04 JAMN/JAMZ 0x00 High Bit B Bus 2 N 6 Z C Bus 2

  5. Exemple Istore (MDR=TOS;Wr; Goto Istore4) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 0x01 4 MPC 9 0x01 8 0x01 8 0x05 0x00 JMPC MIR C Addr J M Alu B 0x04 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  6. Exemple Istore (MDR=TOS;Wr; Goto Istore4) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 0x01 4 0x04 MPC 9 0x01 8 0x01 8 0x05 0x00 JMPC MIR C Addr J M Alu B 0x04 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  7. Exemple Istore (PC=PC+1;fetch; Goto Istore6) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 0x04 4 0x04 MPC 9 0x01 8 0x01 8 0x04 0x00 JMPC MIR C Addr J M Alu B 0x04 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  8. Exemple Istore (TOS=MDR; Goto Main1) Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 0x04 4 0x07 MPC 9 0x02 8 0x01 8 0x04 0x00 JMPC MIR C Addr J M Alu B 0x04 Arrivée de la donnée.Lecture déclenchée dans Istore4 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

  9. Résultat Memory control signals (rd,wr,fetch) 3 4 to 16 Decoder 0x04 4 0x07 MPC 9 0x02 8 0xXX 8 0x04 0x00 JMPC MIR C Addr J M Alu B Arrivée de la prochaine instruction. 0x07 JAMN/JAMZ High Bit B Bus 2 N 6 Z C Bus 2

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