Basic Structure of Computer

1. Basic Structure of Computer • Introduction of computer system & its sub-modules • Basic organization of computer & block level description of the functional units • Von Neumann model • Introduction to buses & connecting I/O devices to CPU & memory • Asynchronous & synchronous bus, PCI, SCSI

2. Computer Organization & Architecture

4. Structural/functional view of a computer

7. Control mechanism Operating environment (source & destination of data) Data movement apparatus Data processing facility Data storage facility Fig: A Functional View of the Computer

8. Communication Lines Peripherals • COMPUTER • Storage • Processing Fig: The Computer

10. COMPUTER COMPUTER Input/ Output Main Memory System interconnection Central Processing unit Fig: The Computer: Top-level Structure

11. COMPUTER Memory I/O System bus CPU CPU Registers Arithmetic & Logic unit Internal CPU interconnection Control unit Fig: The Central Processing Unit (CPU)

12. CPU ALU Registers Internal bus Control unit CONTROL UNIT Sequencing logic Control unit Registers & decoders Fig: The Control Unit Control memory

13. Von Neumann Model

18. Interconnection Structures

19. Fig: Computer Modules

25. The interconnection structure must support the following types of transfers: • Memory to Processor • Processor to Memory • I/O to Processor • Processor to I/O to or from memory

28. Fig: Bus Interconnection Scheme

31. Control Bus Used to control the access to & the use of data & address lines Typical control lines include • Memory read/write • I/O read/write • Transfer ACK • Bus request/grant • Interrupt request/ACK • Clock • Reset

33. Multiple-Bus hierarchies

37. Fig: High-performance architecture

39. Elements of Bus design

40. TypeBus Width Dedicated Address Multiplexed Data Method of ArbitrationData transfer Type Centralized Read Distributed Write Read-modify-write Timing Read-after-write Synchronous Block Asynchronous Elements of Bus Design

44. Synchronous Timing Diagram

45. Asynchronous Timing • Occurrence of one event on a bus follows & depends on the occurrence of previous event.

46. Asynchronous Timing – Read Diagram

47. Asynchronous Timing – Write Diagram

49. PCI(Peripheral Component Interconnect)