Structure of Computer Systems

1. Structure of Computer Systems Course 12 RISC architecture

2. CISC v.s. RISC • CISC – Complex Instruction Set Computer • RISC - Reduced Instruction Set Computer • Historical perspective: • at first computers had a limited instruction set because of technological limitations (number of switching elements was limited) • as integration technology improved: • more instructions were included in the set of a computer • more complex operations implemented in instructions => more complex instructions • consequences: • CPU became more and more complex • CPU became slower (relative to the clock frequency) • higher CPI and limited clock frequency

3. CISC • Reasons for complex instruction set computers • more powerful instructions • e.g. floating point arithmetic instructions • assembly language instructions closer to high level language instructions • e.g. loops, complex conditional jumps • more complex addressing modes, as support for complex data structures • addressing: indexed, based, mixed, scaled, etc. • Benefits: • easier programming in assembly language • less instructions needed to write an application • easier compilation of high level languages • support for complex data structures

4. CISC • Statistical measurements (during the ’70s) • which instruction types are more often used in different types of applications ? • does the programmers use the available complex instructions? • Surprising results • programmers prefer simple instructions • complex instructions are used just occasionally, for some very specific operations (e.g. sine, arc tang. log, exponential, etc.) • most of the time the processor is executing simple instructions from a limited set • Conclusion: • the speed limitation caused by a complex instruction set is not justified • let’s do things simpler and faster

5. RISC • RISC = Reduced Instruction Set Computer • Principle: sacrifice everything for speed • reduce the number of instructions – make CPU simpler • get rid of complex instructions, which may slow down the CPU • use simple addressing modes – less time spent to compute the address of an operand • limit the number of accesses to the memory • if a given operation cannot be executed in one clock period than do not implement it in an instruction • extensive use of pipeline architecture – in order to reach CPI=1 (one instruction per clock period)

6. RISC - Main features • limited number of instructions in the instruction set: • 30-40 instructions v.s 100-200 in case of CISC • no complex instructions • every instruction executes only one operation • instructions have fixed format • fixed length • few combinations of fields inside the instruction code • instructions executed in one clock period (except Load and Store instructions) • through intensive use of pipeline architecture • every instruction have the same number of pipeline stages

7. RISC - Main features • Increased set of general purpose registers • e.g. 32-64 registers • instructions operating with registers are executed in the shortest time • compensate the lack of instructions operating with the memory • Use of multiple register sets • fast and easy context switch • use of register set windows

8. RISC - Main features • Only two instructions operate (have access) to the memory locations: • Load – read data from the memory into a register • Store – write the data from a register into the memory • Load and Store instructions require two accesses to the memory: • one to read the instruction code • one to read or write the data • Load and store instructions are the only instructions which are executed in two clock periods • all the other instructions from the set are operating with registers or a register and a constant

9. RISC - Main features • Hard to write applications in assembly language • lack of more powerful instructions and addressing modes • A program on a RISC is more optimized than the same program written on a CISC • only those operations are used which are strictly necessary • More effort for programming, less time in execution • it is worth to have a greater time spent on programming if at the end the program will be executed many times in a shorter time !?

10. RISC - Main features • The CPU implemented in pure hardware (no microprogramming) • instructions are decoded and executed using hardware components • higher speed less execution steps • Compilers are more difficult to implement

11. RISC v.s. CISC

12. Performance of RISC v.s. CISC CISC: less 4-100 long execution time = no_instructions*CPI*Tclk RISC: more 1 short • Hard to tell which is the best • A combination of CISC and RISC may be the solution: • RISC inside, CISC outside – see Pentium processors • complex instructions translated into simple (RISC) instructions

13. Examples of RISC architectures • Academic implementations: • RISC I si II – Berkley University (prof. Patterson, 1980) • MIPS – Univ. Stanford (prof. Hennessy, 1982) • First commercial implementations • IBM 801 – compania IBM (1975) • ALPHA – compania DEC • SPARC – Sun Microsystems (1987) • General purpose processors: • PowerPC – IBM si Motorola • ARM architecture

14. Applications of RISC architectures • Powerful Workstations • used for engineering purposes (ex. Sun station) • High-end graphical stations • used for simulation, animation, etc. • Microcontrollers • used for control applications and peripheral devices • Digital signal processors • used for signal processing • Mobile devices • iPAD, tablet, support for Android systems

15. RISC architecture examplesMIPS • MIPS – • Microprocessor without Interlocking Pipe Stages or • Million Instruction per Second processor: • developed by Prof. Hennessy at Stanford University (1982) • a classical pipeline architecture used as reference for teaching basic concepts about computers • features: • 32 internal registers • reduced instruction set • instructions with fixed length (4 bytes); types: R,J, I • 3 operands instructions (source, destination, target) • (see a previous course for details)

16. RISC architecture examplesMicrocontrollers • Microcontroller • all components of a micro-computer system in a single integrated circuit: • CPU • program memory • data memory • parallel I/O ports • serial ports • timers, counters • converters: ADC, DAC, PWM • watchdog • used for control applications: • monitoring • feedback control

17. Data memory 0 Ports area Ports area General registers General registers User data area User data area 1Fh Bank 0 Bank 1 2, 3 RISC architecture examplesMicrocontrollers • Example PIC16Fxx • CPU – simple, RISC architecture • Instruction format – fixed, 14 bits/instruction • only 35 instructions • data format: 8 bits • Internal memory – inside the chip - Harvard architecture – data separated from instructions • data memory – 368 bytes SRAM, organized on banks • instruction memory – 8kinstructions • 256 bytes EEPROM (non-volatile memory) • Interfaces: • serial UART and SPI • Convertors: 10 bits ADC with 8 channel multiplexer • 3 timers • parallel ports • ICD – In Circuit debug functionality • Package: 28,40 or 44 pins

18. RISC architecture examplesPowerPC • PowerPC = Performance Optimization With Enhanced RISC – Performance Computing • designed as a competitor for the Intel X86 processor family • developed by Apple, IBM and Motorola (1991) as an open architecture • extension of the IBM’s Power architecture • RISC and superscalar architecture • initially intended for PCs, now used for embedded and high performance computers • 32 and 64 bit processors • many versions: PowerPC 601, 602, 604, 620,740, 74000 • computers made with PowerPC: • Macintosh, Apple • RS6000, (RISC System 6000), IBM • embedded computers