A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms

1. A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms Custom Integrated Circuits Conference (CICC) 2005 Michael S. McCorquodale, Ph.D.Mobius Microsystems, Inc.

2. Outline • Introduction • Background • Clock synthesizer reference oscillator and architecture • Experimental results • Conclusions and future work

3. Introduction

4. Introduction • Much recent work exploring alternative technologies to XTALs for clock generation and frequency synthesis • MEMS microresonators • FBAR • Insufficient exploration of all-Si CMOS approaches • Build on recent work in free-running and open-loop compensation of LC oscillators as frequency references for clock generation

5. Introduction • Goals • Develop an accurate and stable clock synthesizer without an external frequency reference (i.e. XTAL or ceramic resonator) • Develop a clock synthesizer with very low frequency scaling latency • Develop a clock synthesizer with very low start-up latency • Characterize performance over PVT • Demonstrate in a multi-chip module • Approach • Explore free-running RF LC oscillators as frequency references • Utilize a “top-down” synthesis architecture

6. Background

7. Architecture • Reference oscillator • Free-running high-QLC oscillator at a high frequency • Simple frequency trimming interface • Open loop compensation to stabilize over PVT • Very low phase noise • Very low start-up latency • Clock synthesis • Divide down to target clock frequencies • Decrease phase noise by 20log10(N) for divide by N

8. Ro _ RC RL + -gm + ic v i _ _ + Ro L C ic(t) i(t) gm0 t t Background • Resonant frequency • Sources of frequency drift • Real losses: RL and RC • Frequency modulation from harmonic content of driving amplifier • Filter response of LC network and amplifier output resistance

9. fo fmax No oscillation fmin gm gmo Background • fo vs. gm relationship • gmo → minimum gm for start-up • fo → decreases as gm increases (harmonic content increases) • fmin → approached as harmonic content approaches square wave • Can utilize harmonic modulation to self-compensate drift by modulating gm through bias current

10. Clock Synthesizer Reference Oscillator and Architecture

11. 250 215 215 430 430 2.5m 0.53 0.53 0.53 0.53 0.5 0.5 Reference Oscillator R • Complementary cross-coupled architecture with PMOS tail for low phase noise • Bias current, temperature dependent and scaled by ~10x in mirror • Resistor divider self-biases control voltage and reduces VDD sensitivity • vcal trims frequency • Reset transistors disable oscillator MRp R MRn 6.1nH 50kW +out out- vcal 300mA 50kW 0.8-2.5pF 0.8-2.5pF 3pF MRn R

12. 1.056GHz 528MHz R 50MHz vcal EN0 66MHz EN1 Architecture ÷2 ÷10 Out BUF 1 0 S ÷8 Out • “Top-down” or divisive architecture reduces phase noise and period jitter of reference oscillator by 20log10(N) and sqrt(N) • RF reference oscillator can be started with low latency • Any available frequency can be selected asynchronously: low scaling latency

13. Experimental Results

14. Die Micrograph • Fabricated in IBM’s 0.18mm 7RF-CMOS process • Core macro size: <0.4mm2 • Test macros populate periphery • Output drivers drive 10pF with 100ps rise/fall times at 20mArms • Wire-bonded and characterized in 16-pin ceramic DIP • Au studs for flip-chip module assembly

15. Temperature and Voltage Drift VDD±10% • 25°C: ±0.17% • 100°C: ±0.33% Temperature • 0 – 70°C: ±0.75% • -40 – 100°C: ±1.5% PVT Total • Best: <±1% • Worst: ~±1.5% Temp. compensation • Under-compensated • 1.6mV/°C, R2 = 0.9984

16. 3.2ms Start-up Latency • Measured 3.2ms start-up latency from leakage only power state • Latency originates primarily from bias start-up time • Bias circuitry can be modified to reduce latency to ~ns

17. Period Jitter • Measured with Agilent Infinium 4GSa/s scope • 250k samples per edge • 66MHz clock measurement shown • RMS jitter determined by removing trigger jitter

18. Performance Summary

19. Conclusions and Future Work

20. Conclusions and Future Work • Demonstrated a self-referenced LC clock synthesizer with no external reference • Low jitter and scaling/start-up latency • Low overall drift, though drift under-compensated • Temperature compensation correction linear • Alternative compensation techniques already in Si • Very high total accuracy over PVT to be reported soon • Potentially an all-Si approach to stable and accurate clock synthesis • Never underestimate what can be done with CMOS alone

21. Questions welcome