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H. Watanabe, ECE, NCTU , Taiwan

Importance of Interface on device characterization/operation “Quantitative Discussion on Gate Current”. H. Watanabe, ECE, NCTU , Taiwan. Source of this talk:. [1] H. Watanabe, et.al, IEEE TED 53 , 1323-01330, 2006. [2] H. Watanabe, et.al, IEEE TED 57 , 1129-1136, 2010 .

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H. Watanabe, ECE, NCTU , Taiwan

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  1. Importance of Interface on device characterization/operation“Quantitative Discussion on Gate Current” H. Watanabe, ECE, NCTU, Taiwan Source of this talk: [1] H. Watanabe, et.al, IEEE TED 53, 1323-01330, 2006. [2] H. Watanabe, et.al, IEEE TED 57, 1129-1136, 2010. [3] H. Watanabe, IEEE TED 57, 1873-1882, 2010. H. Watanabe, ECE, NCTU

  2. What is Current? Wide enough to measure the current Electrode for TEST Material for CG (Poly, Silicide, Metal?) Studied Dielectrics (tunnel oxide, IPD and so on) SUB, or Poly Tunneling is integrated in space to become a tunnel current. In actual devices, the spatial integration is invalid. SUB Electrode H. Watanabe, ECE, NCTU

  3. What is Current? Even though area is large, trap-assisted leakage is a local issue. H. Watanabe, ECE, NCTU

  4. On Chip In Labo 20 nm 100 um x 100um 100nm x 100nm G 20 nm Gate G D D S S Greater Gate Current to be measurable. Gate current itself is an issue, but too small to be “usually” measurable. Limit of equipment Too small… H. Watanabe, ECE, NCTU

  5. In Labo 100 um x 100um 100nm x 100nm 10nm Gate D S Greater Gate Current to be measurable. Stress-Induced Leakage Current (SILC) Limit of equipment Too small… H. Watanabe, ECE, NCTU

  6. In Labo 100 um x 100um 100nm x 100nm 10nm 1-order Gate D S Greater Gate Current to be measurable. Stress-Induced Leakage Current (SILC) “Local Trap” Limit of equipment Too small… H. Watanabe, ECE, NCTU

  7. On Chip In Labo >10 nm 100 um x 100um 100nm x 100nm >10 nm G 10nm Gate G D D S S Greater Gate Current to be measurable. Trap-enhanced Tunneling: measurable Limit of equipment Too small… H. Watanabe, ECE, NCTU

  8. On Chip >10 nm >10 nm G G G D D S S “Local Trap” H. Watanabe, ECE, NCTU

  9. Motivation of this talk Trap-related Gate Leak should be focused for this aim. Overview of analytical method for this aim. Gate Leak H. Watanabe, ECE, NCTU

  10. Dielectric Scaling in Electron Devices Is 0.5nm a limit? H. Watanabe, ECE, NCTU

  11. Dielectric Scaling in Electron Devices Interface InterFaceTransition Layer is becoming dominate dielectric. H. Watanabe, ECE, NCTU

  12. Muller, Nature ’99 EELS Electron-energy loss spectroscopy O O O Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si O O Si Si Si Si Si Si Si O Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si O O Si Si Si Si Si Si Si Si Si Si Si Si O Si Si Neaton, PRL ’00 IFT layer = atomistic interface + penetration H. Watanabe, ECE, NCTU ~4Å

  13. Literature of IFT layers Limit(?) of EOT is 0.5nm. H. Watanabe, et.al, IEEE TED 53, 1323-01330, 2006. H. Watanabe, ECE, NCTU

  14. Tunnel mass vs IFT Layer Neglecting IFT IFT IFT Tpure Tpure Tox =Tpure + 2IFT Tox= Tpure Tunnel Current Under-estimated H. Watanabe, ECE, NCTU

  15. Tunnel mass vs IFT Layer Neglecting IFT IFT IFT Tpure Tpure M. Stadele, J. Appl. Phys. 93, 2681, 2003 H. Watanabe, IEEE TED53, 1323, 2006 Over-estimated H. Watanabe, ECE, NCTU

  16. Literature of Tunnel Mass H. Watanabe, ECE, NCTU

  17. Model of IFT layer H. Watanabe, IEEE TED (2006) Tall Tpure Gradual Energy Gap (EG) Change Gradual Dielectric Const. (K) Change H. Watanabe, ECE, NCTU

  18. Impact of IFT Layers Positive VG case Negative VG case H. Watanabe, ECE, NCTU

  19. Gate Leak    All IFT related models are considered in calculation. Entire CV & JV are fitted at the same moment. CV-fitting • Thickness  • Tunnel Mass  • JV-fitting Comparison with exp. TOX H. Watanabe, ECE, NCTU

  20. Expansion to Alloy model Gradual Energy Gap (EG) Change A = HrO2 B = Al2O3 C = Si3N4 A = ZrO2 B = Al2O3 C = Si3N4 A = Si B = O C = N Ex) Gradual Dielectric Const. (K) Change A δ β γ α C B H. Watanabe, ECE, NCTU

  21. Expansion to Alloy model (SiO2)1-X(Si3N4) X Gradual Energy Gap (EG) Change A = Si B = O C = N A simplest case Ex) Gradual Dielectric Const. (K) Change Si A 4 δ 2 β SiO2 Si3N4 3 1-x γ α 1 x O C B N H. Watanabe, ECE, NCTU

  22. Stoichiometric Alloy Model (SiO2)1-X(Si3N4) X (Exp. Sample) A = Si B = O C = N Check by Exp. A simplest case Ex) Si A 4 δ 2 β SiO2 Si3N4 3 1-x γ α 1 x O C B N AR-XPS H. Watanabe, ECE, NCTU

  23. Stoichiometric Alloy Model (SiO2)1-X(Si3N4) X Check by Exp. From [O]at and From [N]at are equivalent. AR-XPS H. Watanabe, ECE, NCTU

  24. Stoichiometric Alloy Model (SiO2)1-X(Si3N4) X Bonding-Rate: Change the view point: From “Atoms” to “Bonding”. Lucovsky, SSDM96 Yasuda, SSDM01 H. Watanabe, ECE, NCTU

  25. Stoichiometric Alloy Model EG=EGOX(1-R)+EGSiNR Bonding-Rate: Lucovsky, SSDM96 Yasuda, SSDM01 K=KOX(1-R)+KSiNR H. Watanabe, ECE, NCTU

  26. Further Expansion H. Watanabe, ECE, NCTU

  27. Expansion to Off-Stoichiometry “Stoichiometric” Si “Off-stoichiometric” O N What is ? H. Watanabe, ECE, NCTU

  28. Dangling-Bond (DB) conc. Si O N Suppose: DB Local Trap H. Watanabe, ECE, NCTU

  29. DB Yield is supposed to be very small. is measurable. has a distribution along depth. Once we know , we can obtain the profile of DB. H. Watanabe, ECE, NCTU

  30. DB from Si-N • Si-DB is generated where N is removed from Si-N bond. • N-DB is in lower level. with N incorporated Si Si-DB N-DB Kato, ICPS-28, 2006 H. Watanabe, ECE, NCTU

  31. Band Structure Trap Levels (DB) Si More N EG=EGOX(1-R)+EGSiNR VBA=VBAOX(1-R)+VBASiNR Si3N4 (x=1) Oxide Incorporate (SiO2)1-X(Si3N4)X SiO2 (x=0) More Ox H. Watanabe, ECE, NCTU

  32. Barrier Modulation by trapped charge Suppose: trap (DB) level above Fermi level is charged positive. IFT Barrier Lowering Electron tunneling n poly + p - Si Hole tunneling @ Negative V G IFT Barrier Increasing H. Watanabe, ECE, NCTU

  33. Extraction of YDB CV-fitting with YDB Only YDB modulates CV-curve, since Tphys, [N]- and [O]-profiles are obtained by AR-XPS. Smaple-1 Smaple-2 Smaple-3 Smaple-4 H. Watanabe, ECE, NCTU

  34. Hole Tunnel Mass Assume: Hole Tunnel Mass ( is a parameter. 23% 31% Electron 40% 31% EXP.: Muraoka, JAP94 Tunnel masses for electrons & holes are the same, 0.85m0. H. Watanabe, ECE, NCTU

  35. Trap-assisted tunneling (TAT) Assume: Cross-section, , is a parameter. Trap DDT DT Tunneling Prob.: TAT D1 D2 . TAT DT H. Watanabe, ECE, NCTU

  36. Trap-assisted tunneling (TAT) Assume: Cross-section, , is a parameter. TAT vanishes while  is less than 1E-15cm2. H. Watanabe, ECE, NCTU

  37. CV-JV Fitting Result Enhanced Direct Tunneling H. Watanabe, ECE, NCTU

  38. Single Electron Sensitive 3D device simulator • Put trap in 3D device structure. Positive charge Trap Trap Gate Area: 30nm x 30nm H. Watanabe, “Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap”, IEEE TED., vol. 57, pp. 1873-1882, 2010. H. Watanabe, ECE, NCTU

  39. Gate Area: 30nm x 30nm Trap (Positive Charge) Positive Charge Vd 0V H. Watanabe, ECE, NCTU

  40. Conclusions • Trap-related gate leak is smallest measurable current. • To make sure tunnel mass, IFT layers is carefully considered. • Dangling Bond Yield is introduced. • Enhanced Direct Tunneling is discovered, which is a candidate for the smallest trap-related current. • Today’s device engineering already detected the foot-print. • Data retention degradation from 10-years to ½ year. H. Watanabe, ECE, NCTU

  41. Thanks for your attention. • Co-authors of related papers: • D. Matsushita, • K. Muraoka, • K. Kato • Author is supported as Phison Electronics Chair Professor. • H. Watanabe, D. Matsushita, K. Muraoka, “Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO2 and Si/SiO2 interfacial transition layers”, IEEE Trans. Elec. Dev. Vol. 53, no. 6, pp. 1323-1330, 2006 • H. Watanabe, D. Matsushita, K. Muraoka, and K. Kato, “Universal tunnel mass and charge trapping in [(SiO2)1-x(Si3N4)x]1-ySiy film”, IEEE Trans. Elec. Dev., vol. 57, no. 5, pp. 1129-1136, 2010. • H. Watanabe, “Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap”, IEEE TED., vol. 57, pp. 1873-1882, 2010. H. Watanabe, ECE, NCTU

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