Content:

1. Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic DesignTao LinSchool of EECS, Ohio UniversityMarch 12, 1998

2. Content: • How to build the BDD for a certain function; • Properties of BDD; • Manipulation of BDD; • Application of BDD to the Pass-Transistor design.

3. a E T bc+b’d+c’d b’d+c’d Build a BDD for F: F F=abc+b’d+c’d F=aFa+a’Fa’

4. Build a BDD for F: F F=abc+b’d+c’d a E T F=aFa+a’Fa’ b b F=a(bFab+b’Fab’) +a’(bFa’b+b’Fa’b’) T E T E c+c’d d c’d d

5. Build a BDD for F: Order: a<b<c<d F F=abc+b’d+c’d a F=aFa+a’Fa’ T E b b F=a(bFab+b’Fab’) +a’(bFa’b+b’Fa’b’) T E E T c c E E . . . E T d T T 1 0

6. F b T E c E T a E d T T E 1 0 Re-ordered-BDD (optimal): F=abc+b’d+c’d Order: b<c<a<d

7. Properties of BDD: • The Reduced Ordered BDD (ROBDD) is a canonical form; • The size of the BDD (the number of nodes is exponential in the number of variables in the worst case; however, BDDs are well-behaved for many functions that are not amenable to two-level representations (e.g., XOR);

8. Properties of BDD: • The logical AND and OR of BDDs have the same complexity. Complementation is inexpensive; • Tautology can be solved in constant time. Indeed, F is a tautology if and only if its BDD consists of the terminal node 1;

9. Properties of BDD: • Covering problems can be solved in time linear in the size of the BDD representing the constrains;

10. On the other hand: • BDD sizes depend on the ordering. Finding a good ordering is not always simple; • There are functions for which the SOP of POS representations are more compact than BDD;

11. On the other hand: • In some cases SOP/POS forms are closer to the final implementation of a circuit. For instance, if we want to implement a PLA.

12. a’ a E T 0 1 Manipulation of BDD: a a a T E 1 0

13. ab a T b E E T 1 0 Manipulation of BDD: a a a T E 1 0

14. a+b a E b T T E 1 0 Manipulation of BDD: a a a T E 1 0

15. ab a T E b b T T E E 1 0 Manipulation of BDD: a a a T E 1 0

16. Minimization of BDD: • Identification of isomorphic sub-graphs; • Removal of redundant nodes.

17. F b T E c c E T E T d d d d T E T E T E T E a a 1 0 1 0 1 0 T E T E 1 0 1 0 F=abc+b’d+c’d Minimization of BDD:

18. Minimization of BDD: F b T E c c E T E T d d d d T E T E T E T E a a 1 0 1 0 1 0 T E T E 1 0 1 0 F=abc+b’d+c’d

19. E T d T E 1 0 Minimization of BDD: F b T E c c E T d d T E T E a a 1 0 T E T E 1 0 1 0 F=abc+b’d+c’d

20. E T d T E 1 0 Minimization of BDD: F b T E c c T E d d T E T E a a 1 0 T E T E 1 0 1 0 F=abc+b’d+c’d

21. E T Minimization of BDD: F b T c E d T E a 1 0 T E 1 0 F=abc+b’d+c’d

22. a a’ Realization of the BDD by the pass-transistor design: a VDD T E 1 0 F=abc+b’d+c’d

23. VDD VDD a a’ d d’ c c’ b b’ Realization of the BDD by the pass-transistor design: F b T E c E T d T E a 1 0 F T E F=abc+b’d+c’d 1 0

24. F VDD VDD a a’ d d’ b T E c c’ c E T d b b’ T E a 1 0 T E F 1 0 Realization of the BDD by the pass-transistor design: F=abc+b’d+c’d

25. Conclusion • Pass-Transistor logic design has an extremely simple cell library - just one multiplexer; • BDD representation gives pass-transistor design a powerful synthesis tool; • BDD also provides a rule to judge in which situation we should use pass-transistor logic design and in the other case we should use CMOS.