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I/O Buffer Modeling Class 10 2 lectures

I/O Buffer Modeling Class 10 2 lectures. Prerequisite Reading – Chapter 7 IBIS spec will be used as reference. Additional Acknowledgement to Arpad Muranyi, Intel Corporation. Additional Information. URLs IBIS home page: http://www.eigroup.org/ibis/ibis.htm

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I/O Buffer Modeling Class 10 2 lectures

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  1. I/O Buffer Modeling Class 102 lectures Prerequisite Reading – Chapter 7 IBIS spec will be used as reference Additional Acknowledgement to Arpad Muranyi, Intel Corporation

  2. Additional Information • URLs • IBIS home page: http://www.eigroup.org/ibis/ibis.htm • IBIS 3.2 spec: http://www.vhdl.org/pub/ibis/ver3.2/ • IBIS-X: http://www.eda.org/pub/ibis/futures/ • Tools • Golden Parser: http://www.eda.org/pub/ibis/ibischk3 • Visual IBIS editor, SPICE-to-IBIS tool on IBIS web site. We will use this free tool. http://www.mentor.com/hyperlynx/visibis.cfm I/O Buffer Modeling

  3. Key Topics • What is a model? • Importance of accurate models • Types of buffer models • IBIS and the portions of an IBIS model • How model data is generated • How to calculate VOL and VOH from a model • Package modeling in IBIS • IBIS HSPICE example • Bergeron diagrams I/O Buffer Modeling

  4. Theories, Modeling, and Reality “I take the positivist viewpoint that a physical theory is just a mathematical model and that it is meaningless to ask whether it corresponds to reality. All that one can ask is that its predictions should be in agreement with observation. “ 1 1 Steven W. Hawking, September 30 1994, Public Lecture on “Time and Space” • Electrical models can be derived in two ways • From physical structures and properties • From observed behavior • It is irrelevant whether the electrical models correspond to physical reality. • It only needs to predict behavior. • Hence all models are behavioral I/O Buffer Modeling

  5. ? ? What is a Model? • Electrical representation of a physical device • For example, a transmission line can be modeled as: • A package can be modeled as a combination of transmission lines and lumped elements. • An input or output buffer can be modeled in various ways as well. I/O Buffer Modeling

  6. Importance of Accurate Models • T-lines, package, connectors, vias, return paths, etc. can all be modeled to extreme detail, but if the input (stimulus) is not accurate, it’s wasted. • Garbage in, garbage out. • It is extremely important for engineers to understand the origins of model data, be familiar with modeling types and limitations, and double-check models, whether they create them or they receive them from someone else! • Also, know how your tool uses model data! I/O Buffer Modeling

  7. How do we model I/O buffers? Description Intellectual Property SimulationSpeed “Sweep-ability” RHigh Linear Models RS Very Little Fast Very RLow More detail BehavioralModels Linear or non-linearI-V and V-t data Little Fast Somewhat All buffer details including driving transistors, pre-driver circuitry, receiver diff. amp, etc. TransistorCircuit / Netlist Lots Slowest limited I/O Buffer Modeling

  8. Basic C-MOS Buffer Model Output / Driver Input / Receiver Pull-upDevice ESD Diodes+Inherent Diodes in Transistors Pull-downDevice Pad Capacitance I/O Buffer Modeling

  9. r r load source V(load) V(source) 0 Vlaunch 0 Time N ps Vlaunch V(load) V(source) Zo Vlaunch rload Vs Rs TD = N ps 0 Vs Vlaunch(1+rload) Rt Time 2N ps Vlaunch rloadrsource Vlaunch(1+rload +rload rsource) 3N ps Vlaunch r2loadrsource Vlaunch(1+rload+r2loadrsource+ r2loadr2source) 4N ps Vlaunch r2loadr2source 5N ps Review Lattice Diagram Analysis A signal can be determined by just knowing Vlaunch, rload, and rsource plus delay I/O Buffer Modeling

  10. The original assumption was that Vlaunch, rload and rsource are constant in time and linear. Most buffers are not linear. In other words, there is a current dependent voltage that changes with the time varying voltage. We call these “I-V” curve elements instead of resistors, capacitors, or inductors Refining Buffer Assumptions I/O Buffer Modeling

  11. Beginning of Behavioral Buffer Modeling • This was the basis for a buffer specification that was created in the early 90’s called IBIS Consider that Vs is Vs(t) and V is V(t), so Vintial, rload, and rsource are Vinitial(t), rload(t), and rsource(t). Also, the propagation functions can be described in a similar manner. Hence the voltage and current response and for all nodes in the network can be determined by replacing the buffer with the appropriate “I-V” impedance functions and don’t require the actual transistor models for the buffer. I/O Buffer Modeling

  12. IBIS and Other Model Types • IBIS =I/O Buffer Information Specification • The beginnings of IBIS occurred at Intel during Pentium Pro days. Engineers wanted a way to give buffer information to customers, and decided on I-V curves. The initial IBIS spec was created shortly thereafter. IBIS went through many iterations, eventually adding V-t curves (rev 2.1) and other features like staged devices (rev 3.0). The current revision is 3.2. • Other I-V/V-t model types include: • Various simulator vendors have their own internal models. • However most will convert IBIS to their internal format. • We often use controlled switched resistors (V-t curves of sorts) in SPICE. • Colloquial Terminology ~ V-t = V/T = V(t); I-V = I/V = I(V) I/O Buffer Modeling

  13. What is in an IBIS file? • First IBIS is a standard for describing the analog behavior of the buffers of digital devices using plain ASCII text formatted data • IBIS files are really not models, they just contain the data that will be used. Casually they may be referred to as a models but are really specifications. • Simulation tools interpret this behavioral specification to implement their own models and algorithms Key areas of spec I/O Buffer Modeling

  14. Key Portions of an IBIS Model ESD Diodes+Inherent Diodes in Transistors Output / Driver Input / Receiver Pull-upDevice Vcc Package Package Vcc I(V) V(t) I(V) I(V) I(V) V(t) I(V) I(V) Pull-downDevice Vss may be 0V Vss may be 0V Die Pad Capacitance I/O Buffer Modeling

  15. MOS I-V Curves • Impedance of a buffer is dynamic during transitions - between fully open and fully driving (RON). • Example – let’s take a look at a high-to-low transition below. • In the next few slides we will learn how we can model this dynamic V-I characteristic. VGS VCC VOUT (t=0) = VCC VGS (t=0) = 0 Source VT Gate time 0 1 2 3 4 5 Drain ID Saturation Triode (Ohmic) Drain +VDS = VOUT- t=3 Gate ID t=4 +VGS- Source Vcc t=5 t=2 t=0, t=1(no current below Vt) VCC Vss I/O Buffer Modeling Assume pulled up to Vcc at t=0

  16. Generating pull down I-V Data Pull-down I-VMeasurement or Simulation Setup I Driving LOW +I Sweep V–Vcc to 2Vcc V (N-channel curve) Output / Driver Current is positive above Vss per definition if I flows Pull-upDevice on I(V) V(t) I(V) I(V) V(t) I(V) Pull-downDevice off I/O Buffer Modeling

  17. Generating Ground Clamp I-V Data Ground Diode I-VMeasurement or Simulation Setup I Tristate +I V Sweep V–Vcc to 2Vcc Output / Driver Current is negative below Vss per definition if I flows Pull-upDevice on I(V) V(t) I(V) I(V) V(t) I(V) Pull-downDevice off I/O Buffer Modeling

  18. Generating pull up I-V Data Pull-up I-VMeasurement or Simulation Setup I V Driving HIGH +I Vcc Sweep V–Vcc to 2Vcc (P-channel curve) Output / Driver Current is negative below Vcc per definition if I flows. It is desirable to make the curve referenced to Vcc. Will explain later Pull-upDevice on I(V) V(t) I(V) I(V) V(t) I(V) Pull-downDevice off I/O Buffer Modeling

  19. Generating Power Clamp I-V Data Pull up diode I-VMeasurement or Simulation Setup I Power Clamp Tristate V +I Sweep V–Vcc to 2Vcc Current is positive above Vcc per definition if I flows Output / Driver Pull-upDevice on I(V) V(t) I(V) It is desirable to make the curve referenced to Vcc. Will explain next I(V) V(t) I(V) Pull-downDevice off I/O Buffer Modeling

  20. I(V) V(t) I(V) V(t) I(V) V(t) I(V) I(V) I(V) I(V) V(t) I(V) V(t) I(V) V(t) I(V) I(V) I(V) Double Counting Resolution • Sometimes the clamp current is not zero in the range of operation. • Before use in IBIS the clamp current needs to be subtracted. • Below is an example for the ground clamp and pull down data Pull up measurement I Power Clamp I I V Vcc Vcc Vcc Vcc Vcc Pull up curve I/O Buffer Modeling

  21. I-V Curves in IBIS • IBIS uses Vcc-referenced I-V curves for all devices hooked to the power rail (pull-up and high-side diode). • This effectively shifts and flips the I-V curve. • Major reason is so same model can be used regardless of power connection (independent of Vcc). • For example, a 5-V and 3.3-V part can use the same model. Measured Curve IBIS Curve I V I V Vcc Vcc Pull-up Vcc Pull-up Sweep V–Vcc to 2Vcc Driving HIGH +I I Power Clamp Power Clamp I V V I/O Buffer Modeling

  22. Simple model of High/Low drive • The high and low switches are ideally complementary • They switch in opposite senses simultaneously • Real devices have slightly different switching characteristics. I-V I(V) V(t) Controls V(t) for High Curve I(V) V(t) Controls V(t) for Low Curve I-V I/O Buffer Modeling

  23. How to Generate the V-t Data • 4 V-t curves are required • 2 for each switch for high and low switching • Accuracy is improved if Rload is within 20% of the usage model load Pull-up V-t Measurement or Simulation Setup V V VCC VCC Driver VOH VOH + RLOAD (typically 50 ohms) t t Pull-down V-t Measurement or Simulation Setup V V VCC VCC Vcc + RLOAD (typically 50 ohms) Driver VOL VOL t t I/O Buffer Modeling

  24. Why Four V-t Curves? • It is important for the V-t curves to be time-correlated. • The four V-t curves describe the relative switching times of the pull-up and pull-down devices. NMOS is completely OFF PMOS is completely ON PMOS begins turning OFF NMOS begins turning ON VCC VOH All V-t curve measurements or simulations are started at time zero. VOL NMOS begins turning OFF NMOS is completely ON PMOS begins turning ON PMOS is completely OFF I/O Buffer Modeling

  25. More on IBIS transition time • Two ways to synchronize switch • Build delay into curves • Use version 3.1 Scheduled drivers • Make sure the total transition time to settling is shorter that half the period. Start of bit time I/O Buffer Modeling

  26. PVT Corners • PVT = Process, Voltage, Temperature • Models in the past have historically been built at the “corners.” All buffer characteristics are considered dependent parameters with respect to PVT. • Fast Corner = Fast process, high voltage, low temp. • Slow Corner = Slow process, low voltage, high temp. • These can be entered into an IBIS model in the “min” and “max” columns. • Fast/strong in the max column • Slow/weak in the min column • In recent generations we have found that just providing fast and slow corners does not adequately cover all effects. In these cases other model types can be given (e.g., “max ringback” model). • Compensated buffers explode the combination of required buffer corners. • They use extra circuits to counteract (compensate) PVT effects • This makes PVT and buffer characteristics independent parameters. I/O Buffer Modeling

  27. “Envelope” or “Spec” Models • Historically, we have repeatedly predicted buffer strength and edge rates incorrectly. • Buffer strengths are often weaker in silicon. • Edge rates are often slower in silicon. • One approach that can be used is to create “envelope” or “spec” models. For example: I V Envelope. All measured curves should fall within these specs. Strong Key point!!!: These spec curves can be given to I/O designers to describe required buffer behavior. Weak V t I/O Buffer Modeling

  28. Issues with spec curve models • These are legal according to the spec. • Sometimes more qualification is required. I V Envelope. All measured curves should fall within these specs. Strong Instantaneously a short Weak Instantaneously an open V t Non-monotonic I/O Buffer Modeling

  29. Example: Create CMOS Model • Given: • Vcc = 2.0 V • Measurement threshold = 1 V; VIL = 0.8 V; VIH = 1.2 V • NMOS RON = 10 ohms • PMOS RON = 10 ohms • All edge rates are ramps of 2 V/ns • Capacitance at the die pad of the buffer = 2.5 pF • Clamps are 1 ohms and start 0.6V above and below rails • PMOS starts turning on 100 ps after NMOS starts turning off (rising edge) • NMOS starts turning on 100 ps after PMOS starts turning off (falling edge) • Will use Mentor Graphic Visual IBIS editor in example • http://www.mentor.com/hyperlynx/visibis.cfm I/O Buffer Modeling

  30. Example: Header information I/O Buffer Modeling

  31. Package definition and pin allocation mysimple_buffer signal001 I/O Buffer Modeling

  32. Model statement • Notice the name “special_IO” is assign to our single pin before. • Many pins and models can specified for single component mysimple_buffer signal001 I/O Buffer Modeling

  33. Construct in this example with a spread sheet Break session to IBIS Edit to view I/V curves Assignment: Use this example and change the pull and pull down curves to 15 ohms. Check with Visual IBIS. Correct VT waveforms. I-V curves I/O Buffer Modeling

  34. The 4 V-t waveforms w/ spec 100ps delay I/O Buffer Modeling

  35. Match V-t and I-Curves • The intersection of the load line of the fixture (specified in the waveform section) and a corresponding I-V curve determines the Voh and Voh that should to be used in the respective V-t section Vdd Vdd I Pull down R_fixture Fixture load line Vdd Vdd Vol More on load lines later V-t I/O Buffer Modeling

  36. End and Ramp • The ramp is specified but the simulator tool can determine whether to use the ramp or the V-t data • The End statement is require • The IBIS 3.1 and 2.1 are spec are actually readable IBIS code and can be view with an IBIS editor. I/O Buffer Modeling

  37. GTL+ on die termination • Recall that a GTL buffer contains pull-down transistors only • No switched PMOS • Many of Intel’s processors and chipsets have started to include termination devices inside the I/O buffer. • This eliminates the stub on the PWB to connect to the termination resistance Vcc On- or off-die resistor for pull-up and termination I/O Buffer Modeling

  38. On-die Termination • One way to include on-die termination is to use superposition and add the termination currents to the diode currents in the clamp sections. • The clamps are always active in an IBIS model, regardless of whether the buffer is driving or receiving. Since the termination is always active, also, this scheme works well. Power Clamp + On-die term.(Put full curve into power clamp section of IBIS model.) I V I Power Clamp I Vcc + V On-diePull-upResistor V Vcc Vcc I/O Buffer Modeling

  39. Package Modeling in IBIS • Three ways to model packages in IBIS: • Lumped R, L, C values in IBIS file • Package models • EBD (Electrical Board Description) • Package models and EBDs follow this convention:[Len=l R=r L=l C=c] • Examples: • Lumped resistor: Len=0 R=50 L=0 C=0 • Capacitor package: Len=0 R=[ESR] L=[ESL] C=1uF • Package trace: Len=1.234 R=0 L=10E-9 C=2E-12 I/O Buffer Modeling

  40. Example: VOL Calculation – Resistor Load Line • The I-V for the resistor load is below Vcc = 2V 50 ohms RLoad I Pull-down I-V curve VccRLOAD 50 ohm load line ZeroVoltage Load lineSlope = -1/RLOAD V Zero Current Vcc VOL I/O Buffer Modeling

  41. Example: VOL Calculation - buffer • Now create the NMOS I-V curve for load line analysis below: ~10ohms I Pull-down I-V curve VccRLOAD V Vcc VOL I/O Buffer Modeling

  42. Example: VOL Calculation • Using the intersection of the NMOS I-V curve and load line, calculate VOL: • The Vol should correspond the Vol in the V-t waveforms Vcc = 2V 50 ohms ~10ohms 50 ohms I Pull-down I-V curve Sanity check and solution: VccRLOAD Vcc = 2V ZeroVoltage 50 ohms Load lineSlope = -1/RLOAD VOL = 0.33 V 10 ohms 50 ohm load line V Zero Current Vcc VOL I/O Buffer Modeling

  43. Example: Calculate VOH • calculate VOH from the intersection of PMOS I-V curve and the resistor load line: • The Voh should correspond to the Voh in the V-T waveforms Vcc = 2V ~10ohms 65 ohms 30 ohms VOH V VCC Example: VOH = 1.5 V Needs to agree with V-T data 30 ohm load line terminated to ground this time) I/O Buffer Modeling I

  44. Using IBIS Models in HSPICE • Use the IBIS file presented earlier (10 ohm up down resistor. • Compare toUsing prior HSPICE example and MYBUF subciruit library and switch case with alters. • New net list name: testckt_ibis.sp 0-2V.33ns r/f full transition time 10 W I/O Buffer Modeling

  45. Recall HSPICE Block Diagram Printed WiringBoard Data generator package package Buffers Receiver I/O Buffer Modeling

  46. Create three libraries for MYBUF • ‘driver’ – source/resistor model • ‘driver_ibis’ – 10 ohm CMOS IBIS model using ramp data • ‘driver_ibis_two’ - 10 ohm CMOS IBIS model 2 V-t curves for rising and falling edges. (4 total) • Good example to show how to use libraries. • In some cases we start with a behavioral model move to a transistor model to fine tune the buffer design and solutions space. • This modularity enables this migration path with minimal impact to the system model. I/O Buffer Modeling

  47. The three alters produces .tr0, .tr1, .tr2 • Before the end statement insert the alter statements • Adjust the pulse source to .333 ns I/O Buffer Modeling

  48. Resistor Source Library • Use delay to synchronize cases • We will force IBIS to start on the 50% point in the bit drive waveform I/O Buffer Modeling

  49. HSPICE IBIS example • This is a simple example. Many more controls are possible • Buffer=2 tells hspice to use an output buffer model • Ramp_fwf and ramp_rwf = 0 means use the ramp • Ramp_fwf and ramp_rwf = 2 means use the 2 V-t curves for each edge • The edges are scaled by 1/10 also to match the resistor/source • What does NINT do? I/O Buffer Modeling

  50. Results: first glance seem not bad I/O Buffer Modeling

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