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KS NOTE Power Study

KS NOTE Power Study. NDK100/ PE Jimmy. Power table -1. Power table -2. H8. 2. VCCXM_ON. M_ON. 1. VCCXA_ON. 9. POWER. aux_ON. TSURUMA. PWR_SW. 8. A_ON. VCCXB_ON. PMH7. B_ON. 5. MPWRGD. BPWRGD. 10. 7. 4. PCI DEVICE. SLP_S3 . SLP_S4. PWR_SW_H8. 14. PCIRST. PLTRST.

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KS NOTE Power Study

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  1. KS NOTE Power Study NDK100/ PE Jimmy

  2. Power table -1

  3. Power table -2

  4. H8 2 VCCXM_ON M_ON 1 VCCXA_ON 9 POWER aux_ON TSURUMA PWR_SW 8 A_ON VCCXB_ON PMH7 B_ON 5 MPWRGD BPWRGD 10 7 4 PCI DEVICE SLP_S3 . SLP_S4 PWR_SW_H8 14 PCIRST PLTRST SB BPWRGD NB CPU_PWRGD (BPWRGDX VR_PWRGD) 13 12 15 CPURST VR_PWRGD ADP 3207 CPU 11 VCCCPUCORE

  5. 1. Insert adapter to system (1) DOCK_PWR19_F&VREGIN19& VCC3SW Power generate process with adapter U12 CV19 Dock_PWR19_F F10 Adapter In F14 VREGIN19

  6. VCC3SW Input output U74 VCC3SW VREGIN19 因此只要power VREGIN19 supply to U74 , 無須控制信號U74產生VCC3SW

  7. VINT19 U13 CV19 VINT19 When DCIN_DRV=H, 打開 U13 and generate VINT19 DOCK_PWR19_F &VREGIN19& VCC3SW Power Sequence

  8. Power on Enable signal generate VINT19 DOCK_PWR19 when adapter insert and U64 detect AC power OK , then generate EXTPWR.

  9. EXTPWR_PMH generate process and Power Sequence EXTPWR 信號 be sent to Q50 產生EXTPWR_PMH . Of course , system need Power VL5 來打開Q50 . VL5 generate process as next page:

  10. VL5 R189 U58 MAX1977_LOD5 Vl5 VINT19 When U58 detect VINT19 OK , 產生 MAX1977_LCDO5 , 再通過R189產生VL5

  11. M1_ON & M2_ON&AUX_ON EXTPWR_PMH M1_ON U72 Control Signal EXTPWR_PMH be sent to U72 , 然后產生Control Signal M1_ON/M2_ON/AUX_ON EXTPWR_PMH M2_ON PWH7 AUXON

  12. M1_ON & M2_ON&AUX_ON Sequence

  13. PWH Control Signal Sequence 這里順便了解一下PWH Control Signal Sequence • System detect EXTPWR OK then generate M_ON & AUX_ON • System detect PWRSTWITCH OK then generate A_ON &B_ON , • 也就是說﹕ • System generate M_ON & AUX_ON before pressing power button • System generate A_ON & B_ON after pressing power button

  14. VCC3M_ON & VCC5M_ON & VCC1R5M_ON & VCC1R2AUX_ON & VCC3AUX_ON

  15. VCC3M & VCC5M Output VCC3M Output VCC5M Enable Signal : VCC5M_ON VINT19 U58 Max1977 VCC3M&VCC5M VCC5M_ON

  16. VCC3M & VCC5M Sequence

  17. MPWRG VCC5M VCC3M When U74 detect VCC3M&VCC5M all OK , then it send MPWRG VCC3M&VCC5M U74 MPWRG VREGIN19 BD4175KVT

  18. MPWRG Sequence

  19. MPWRG Signal generate high signal when the following condition are satisfied. (1) VCC3M_ON& VCC5M_ON High (2) VCC5M Voltage SPEC: 4.311V~4.461V VCC3M Voltage SPEC : 2.793V~2.943V shut down when the following condition are satisfied (3) VCC5M < 4.311V or VCC5M > 4.461V , M_PGS shut down (4) VCC3M> 2.943V or VCC3M< 2.793V , M_PGS shut t down 5M_ON & 3M_ON AND M_PGS VCC3M&VCC5M

  20. VCC1R5M Power Output Control signal VCC5M&VINT19 U57 Max1540 VCC1R5M VCC1R5M_ON

  21. VCC1R5M Sequence

  22. VCC1R2AUX VCC1R2AUX_ON VCC1R5M VCC1R2AUX U35

  23. VCC1R2AUX Sequence

  24. VCC2R5M U30 VCC3M VCC2R5M

  25. VCC2R5AUX & VCC3AUX VCC2R5M Q46 VCC2R5AUX VCC3AUX_ON VREGIN19 U74 VCC3AUX_DRV VCC3AUX Q49 VCC3M

  26. VCC2R5AUX & VCC3AUX Sequence

  27. Summary 以上介紹的Power 是在 Adapter insert system but do not power on 產生的 , 下面介紹Power on 后系統的上電情況.

  28. 2. Power On PWRSWITCH# & PWRSW# & PWRSW_H8# KBC D10 PWRSW# PWRSWITCH# Press Power Button PWRSW_H8#

  29. PWRSWITCH# & PWRSW# & PWRSW_H8# Sequence

  30. Enable signal Diagram PM_SLP_S3# 5 PM_SLP_S3# A1_ON PWRSWITCH 1 PWH7 B1_ON 5 B2_ON ICH_SLP_S3# D10 4 ICH_SLP_S4# PWRSW KBC 2 PWRSW_H8 ICH7 3

  31. ICH_SLP_S3# & ICH_SLP_S4# & PM_SLP_S3# & PM_SLP_S5# Sequence PM_SLP_S3# & PM_SLP_S5# Sequence ICH_SLP_S3# & ICH_SLP_S4# Sequence

  32. A1_ON & B1_ON & B2_ON Sequence

  33. VCC1R8A_ON & VCC1R05B_ON & B_ON & VCC0R9B_ON

  34. VCC1R8A Power Output Control Signal VCC5M & VINT19 U21 VCC1R8A VCC1R8A_ON

  35. VCC1R8A Sequence

  36. VCC1R05B VINT19&VCC5M U57 VCC1R05B VCC1R05B_ON

  37. VCC0R9B & VREF Power Output Control Signal VCC1R8A&VCC5M VCC0R9B DDR2_VREF U21 VCC0R9B_ON

  38. VCC2R5B Q39 U74 VCC2R5B VCC2R5B_DRV B_ON

  39. VCC0R9B & VCC1R05B & VCC2R5B

  40. VCC3B & VCC5B B_ON 通過U74將Q67&Q52打開 to generate VCC3B&VCC5B

  41. VCC1R5B U75 B_ON VCC2R5B_DRV VCC1R5B U60 VCC1R5M

  42. VCCCPUCORE_ON If VCC1R05B & VCC1R5M OK then VTT_PWRG turn high VTT_PWRG AND VCORE_ON B2_ON SHUTDOWN2

  43. VCCCPUCORE VCCCPUCORE If VCCCPUCORE OK , then generate VR_PWRGD

  44. VCCCPUCORE Sequence

  45. B POWER & VCCCPUCORE Sequence

  46. MPWRG & APWRG & BPWRG If VCC3M/VCC5M & VCC3A & VCC3B/VCC5B OK , then pull high MPWRG & APWRG & BPWRG

  47. MPWRG & APWRG & BPWRG Sequence Spec: APWRG to BPWRG is 80-120ms 80-120ms

  48. PCIRST# CPURST# CPUPWRGD=VR_PWRGD AND BPWRG 2 PCIRST VR_PWRGD 2 ICH7 1 CPUPWRGD 4 BPWRG PLTRST ADS CPU 3 CPURST CALISTOGA 7 7

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