Adding the Superset Adder to the DesignWare IP Library

Adding the Superset Adder to the DesignWare IP Library Stevo Bailey

Motivation Technology scaling exacerbates variation and reliability issues Memory circuits have redundancy and error detection/correction schemes Need arises for robust arithmetic datapaths Redundancy, reconfiguration

Addition in Circuits A3 B3 A2 B2 A1 B1 A0 B0 Cin A3 B3 A2 B2 A1 B1 A0 B0 Setup FA G3 P3 G2 P2 G1 P1 G0 P0 FA FA G3:2 P3:2 G1:0 P1:0 FA CLA (Prefix) Blocks Cout S3 S2 S1 S0 Ripple Carry Addition Delay: O(N) G3:0 P3:0 Minimum Parallel Prefix Delay: O(log2N) Prefix Operation: Sum Calculation (not shown): (G1:0, P1:0) = (G1 + P1G0, P1P0) Si = Gi-1:0 XOR Pi

Parallel Prefix Adders Kogge-Stone Brent-Kung Han-Carlson Trade logic depth (delay) for complexity (area and power) Radix 2, fan-in 2

Superset Adder Full Tree Full controllability over prefix nodes

Synopsys Overview Module Compiler Code Module Compiler Optimized VHDL Add to DC Synthetic Library Path Synthetic Library Code Analyze VHDL in DC

Module Compiler Input and Synthesis MCL Code Module Compiler Analysis

Module Compiler Output Module Compiler Output Files Module Compiler Output VHDL

Module Compiler Relative Placement Relative Placement View (manual)

Area Comparison

Delay Comparison

Design Compiler Code TCL Script Synthetic Library Code

Design Compiler 8-bit Superset Adder Schematic

Current Issue How do I get VCS to simulate my adders when they include library components?

Questions?

Adding the Superset Adder to the DesignWare IP Library