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New TOT design for the LAV F.E. electronics

New TOT design for the LAV F.E. electronics. M. Raggi, P. Valente G. Corradi, D. Tagnani LNF electronic service TDAQ Working Group 29/05/2009. Energy deposit in the LAV (Riccardo). Maximum energy deposit into LAV > 20 GeV The core of the distribution extends up to 10 GeV

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New TOT design for the LAV F.E. electronics

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  1. New TOT design for the LAV F.E. electronics M. Raggi, P. Valente G. Corradi, D. Tagnani LNF electronic service TDAQ Working Group29/05/2009

  2. Energy deposit in the LAV (Riccardo) • Maximum energy deposit into LAV > 20 GeV • The core of the distribution extends up to 10 GeV • 80% of deposited energy is confined in a single block • We want to measure with good efficiency energy deposit > 50MeV

  3. Possible PMT working point PMT working point for MIP • Gain ≈ (1-2)x106; Edep=80 MeV; Np.e./MeV=0.3 • Collected charge for MIP QMIP≈5 pC • Signal wdt=20 ns • VMIP= 2*QMIP*50W/20ns = 25 mV PMT max expected signals • No saturation observed in PMT for signals up to 25V • VMAX<2*Q20GeV*50W/20ns = 7 V max expected signal • Variations within different blocks and fluctuations can produce signals of order ≈ 10 V

  4. Immagini del segnale analogico

  5. Read out electronics requirements Requirements • Energy resolution ≈ 10%/√E • Time resolution < 500 ps • Max rate ≈ MHz x ch (will be lower in real life) • Able to manage very large signals ≈10V • Measure energy 20 MeV – 20 GeV xblock range Strategy • Use Time Over Threshold to measure charge • Use Pisa TDC card for the readout (HPTDC) • Use 1 Tell1 x RING to reduce cost

  6. Preliminary results of NINO tests with Pbgl cosmic ray signals

  7. Nino ASIC chip ALICE TOF system • Charge range 0.2-2 pC • Eight channels per ASIC. • Differential input • LVDS output • Output pulse width dependent on the charge of the input signal • Fast amplifier to minimize time jitter, i.e. first stage with a peaking time of 1 ns; • Discriminator threshold in the range 10–100 fC

  8. Schematic of the NINO circuit • Input Stage • Threshold adjust circuit • 4 stages of low gain High BW differential amplifiers. • Pulse stretcher • Output signal width from MRPC varies 2-6 ns • Add 10 ns to out signal width to match HPTDC • LVDS output driver to TDC

  9. The LAV-NINO adapter card • 8 ch lemo input (+4 V -4V dynamics) • Each input is divided by 1, 1/10, 1/100 and sent to NINO • 3x8 output channels into NINO board Single channel layout

  10. Experimental setup LAV adapter + NINO VME READOUTDual Range QDC+TDC(100ps)

  11. NINO dynamic range test • Experimental setup used to test NINO dynamic range: • Time wdt in the range 20-350 ns have been explored • Amplitude range 10-150 mV (20 ns) • Use the NIM signal to: • Evaluate efficiency (scaler) • Measure signal width (Oscilloscope) LVDSto NIM Oscilloscope Pulser FE+NINO Scaler

  12. Range tests results Using square waves we measure the time over threshold of corresponding NINO signals The NINO shows linear behavior up to 350 nsThe intercept of the fit is due to the time stretcher circuit of NINO

  13. Charge vs TOT test setup FE+NINO TDC ADC Amplifier x10 Bridge Discr. Scintillator Discr.

  14. Typical NINO signal with Pbgl input

  15. TDC hit map Signal The trigger on ch 31 shows cross talk @ 10-4 level in TDC Trigger The signal shows cross talk between ch 6 and ch 5 @ 10-3 level (NINO ?) Signal Signal

  16. Signal width VS charge 1.6E-19*3.5E6*0.35*70*10 = 140pC

  17. TOT vs charge fit Limited charge range due to cosmic ray trigger F=P1+P2X+ P3X2 Fit function can be improved

  18. Charge resolution using TOT only TDC LSB 200 ps s1 = 6%s2 = 17.5% AVERAGE RESOLUTION 8.5% Noise contribution high due to 1/100 attenuation used. No correction appliedTDC resolution 200 ps

  19. Resolution VS charge

  20. Conclusion and to do on NINO Max nominal charge in NINO correspond to half a MIP in LAV PMT Threshold range 10-100 fc < 1 p.e. @ 106 gain too low The use of the Pbgl block in the trigger forced the charge to be too high in NINO (can use only 1/100 scale) Charge measurement with a precision <10% can be reached using TOT technique on LAV PMT signals To do list Build an external trigger based on scintillators or use the Pbgl test stand as a trigger system Set the PMT gain near the defined working point (1-2)x106 Enlarge the charge range changing the gain of the PMT

  21. New TOT system for the LAV

  22. Basic Ideas • Build a low cost TOT system with larger dynamic wrt NINO asic • Use commercial devices (not a dedicated ASIC) • Clamp system able to maintain the TOT of original signal (needs very fast low capacitance diodes) • Amplify the signal a bit (x3) to allow correct reduce overdrive and to enlarge signal width (>15 ns) • Compare the amplified clamped signal with a low settable thr to start and stop the LVDS signal • Send an LVDS out to the TDC

  23. Clamp stage: performance simulation • Clamp input signals > 300 mV • Requires very fast low-capacity HSMS-286C-TR1G schottky diodes • HSMS-286C-TR1G diodes can suffer for too much power on it • The power in excess is dissipated using properly dimensioned metal pads on the PCB VOut VIn The clamp maintain the trailing edge time of the original signal! No limit to maximum amplitude of signals to be measured using TOT!

  24. Single channel Layout AnalogOut/2 AnalogInn ClampedOut LVDSOut Comparator x3 Amplifier Clamp stage Thr circuit

  25. TOT resolution improvements TOT with low thr may suffer for noise on long signal tails Adding a pole (T3) to signal tail allow a cleaner definition of trailing edge T1 therefore better definition of the TOT Consequences on dead time to be understood T3 T4 Dead time 0 mV T1 T0 T2 thr Part of the dead time (T2-T1) is recovered by shortening the original signal Original signal Shaped signal Channel is no more considered dead [T1;T2] as it was for the original signal (risky business) Total dead time (T4-T0) increased by (T4-T2)

  26. Board layout submitted • 4 channels prototype board submitted to firm include: • 4 analog input channels • 4 direct analog out divided by 2 • 4 clamped analog out • 4 independent thr adjust trimmers • LVDS out to CAEN TDC • Foreseen studies: • Time stability of clamp trailing edge for large signals • Death time and max rate measurements • Time resolution • Energy resolution using TOT • Efficiency VS thr for MIP signals

  27. 1xTELL 1BOARD F.E. board F.E. board F.E. board F.E. board F.E. board L0 FPGA Eth Gbit TDC 128ch TDC 128ch TDC 128ch TDC 128ch Final readout scheme for VETO For each ring 160 ch 5 board 5x32 ch In 10x32 ch Out VetoRing To L0trigger 16x32 ch Out 8x32 ch In Eth Gbit 256 ch 8 board 1MHz x 2x32Bit x10 ch ~ 640 Mbit Whole LAV system Veto Event Builder <4x1 Gb To ReadoutPc FARM Veto Switch48x1Gb In out <4x1 Gb <1Gb/ring

  28. TELL 1Eth receiver TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD TELL 1BOARD L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA L0 FPGA Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch 6xEth 1Gbit TDC 128ch TDC 128ch 6xEth 1Gbit TDC 128ch TDC 128ch 6xEth 1Gbit 6xEth 1Gbit TDC 128ch TDC 128ch TDC 128ch TDC 128ch TDC 128ch Global L0 layout for LAV Eth receiver under development @ Rome2 Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit Eth Gbit

  29. # of electronics components • Assumptions • 1 scale for the whole dynamic range • 32 ch per front end card • 2 channels into TDC for each input (100% redundancy)

  30. Naïve cost estimate • Does not include 12-24 crates + power supply • * Cost is an upper limit driven by the request of on board FPGA (real cost estimate needs final board design) ** Cable type to be defined cost is just a guess • Final cost will be < 300K€

  31. Conclusions • The use of NINO in LAV electronic seem difficult • Dynamic range too small max 2 pC thr 10-100 fC • 3xN channels to allow 1000 range • Strange behavior for high charge signal (not understood) • New TOT device: • Much higher dynamic range (commercial electronic) • High performance clamping stage included • No need for multiple scales • Time scale for new prototype • Project submitted to firm on Monday this week • PCB delivery expected @ beginning of June • Test foreseen during July as soon as ANTI-A1 is finished

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