Christine HU-GUO (IPHC-Strasbourg)

1. R&D Collaboration betweenDUT(Dalian University of Technology)& IPHC (Institut Pluridisciplinaire Hubert Curien) Outline • Presentation of R&D activities of the CMOS sensor group at IPHC • Introduction of the Institute of µ-electronics at DUT • R&D collaboration program Christine HU-GUO (IPHC-Strasbourg)

2. IPHC: MAPS for Future Vertex Detectors • Since 1999, the CMOS sensor group at IPHC led by Marc Winter has worked on R&D of MAPS (Monolithic Active Pixel Sensors) for future vertex detectors and imagers for bio-medical applications • MAPS is also called "CMOS" sensors • The actual group is composed of: • 5 physicists + 3 PhD students • 10 microelectronic designers + 4 PhD students • 4 testing engineers IPHC-DUT christine.hu@ires.in2p3.fr

3. MAPS: Physics Motivations • Flavor tagging takes growing importance in understanding the dynamics underlying • Heavy ion and particle physics phenomena  b, c, t tagging with high efficiency & purity • Ex: ILC physics program: • Benefit from knowledge of e+ e- collisions at energy frontier • Identify the details of the final state  Allow to understand the elementary processes in the collision • Vertexing & Tracking: • Need excellent reconstruction of secondary vertices • Granularity & low material budget • Need precise measurement of the momenta of tracks • Improve the tracker precision by an order of magnitude w.r.t.existing state of the art IPHC-DUT christine.hu@ires.in2p3.fr

4. MAPS: R&D Motivations • Aim for an ultra-light, very granular, poly-layer Vertex Detector installed very close to the interaction point • Demanding running conditions (occupancy, radiation) !!! • Existing technologies are not adequate: • CCD (SLD): granular and thin BUT too slow and not radiation hard • Hybrid Pixel Sensors (Tevatron, LHC): fast and radiation hard BUT not granular and thin enough • CMOS sensors are expected to provide an attractive trade-off between granularity, material budget, radiation tolerance and speed IPHC-DUT christine.hu@ires.in2p3.fr

5. R.T. Main Features of MAPS • Integrate the sensing element and the processing electronics on the same substrate by using a standard CMOS process • p- type low- resistivity Si hosting n- type "charge collectors" • Signal created in epitaxial layer of low-resistivity silicon (low doping) • p-EPI 10-15 µm thick • Q ~80 e- h /µm  signal <~ 1000 e- • Excess carriers propagate (thermally) to diode formed by n-well/p-EPI junctionwith help of reflection on boundaries with p-well and substrate (high doping) • Collection time < 100 ns • Charges are converted to voltage at capacitance of the sensing diode • Active volume is underneath the read out electronics • 100 % fill factor IPHC-DUT christine.hu@ires.in2p3.fr

6. Advantages of MAPS • Signal processing micro-circuits integrated on sensor substrate (system-on-chip) • compact, flexible • Sensitive volume (EPI layer) is 10-15 µm thick • thinning to 30 µm permitted • Using standard, massive production, CMOS fabrication technology • Cheap, fast turn-over  Attractive balance between granularity, material budget, radiation tolerance, readout speed and power dissipation IPHC-DUT christine.hu@ires.in2p3.fr

7. MAPS: Achieved Performances • Detection efficiency ~ 99.9% • N ~ 10-15 e-, S/N ~ 15 – 30 • Spatial resolution ~ 1 / 1.5 / 2 / 3 µm (pitch ~ 10 / 20 / 30 / 40 µm) (for analogue output) • Sensor could be thinned down to ~ 50 µm • Radiation tolerance: • Total ionizing dose tolerance: >~ 1 Mrad (design ”rad. tol.” pixels, T < 0 ) • Non-ionizing radiation: 1012–1013 neq/cm2 (function of pitch, sensitive volume and Temp) • Room temperature operation • Minimize cooling requirement IPHC-DUT christine.hu@ires.in2p3.fr

8. MAPS: Main R&D Direction (Detection & Signal Processing) • High readout speed, low noise, low power dissipation, highly integrated signal processing architecture: • Analogue part (charge collection, pre-amplifier, CDS,…) inside pixel • Mixed (ADC) and digital (sparsification) µ-circuits integrated inside pixel or aside of active surface • Radiation tolerance: • Minimize dark current (after irradiation) • Room temperature operation • Specific layout • Design against Latch-up • Specific layout and proper technology IPHC-DUT christine.hu@ires.in2p3.fr

9. MAPS: Main R&D Direction(Technology) • Optimal Fabrication Process: • EPI layer thickness & doping parameter • Dark current (yield) • Number of metal layers • Cost & life time of process • Study of thinning Procedure: • Minimal thickness • Mechanical properties • Individual chips rather than wafer  yield • Need to have an access to process information from foundries and post-processing industry BUT due to small production volume  difficult!! • That is why we need collaboration with universities and research institutes who have such experiences and equipments  DUT IPHC-DUT christine.hu@ires.in2p3.fr

10. L1 -Power regulation L2 -Digital circuits L3-Analog circuits MAPS: Main R&D Direction(Technology) R&D on technology is also an important step for 3DIT • What is 3DIT? • Stacking several circuit layers • thinned down to a few µm • Interconnection between layers: TSV • Diameter ~ µm  3DIT: dreaming technology for trackers? 3D circuit with sensor and several circuit layers (total thickness less than 100 um) IPHC-DUT christine.hu@ires.in2p3.fr

11. Institute of Microelectronics at DUT • Main R&D activities (group leader: Zhen-an Tang) • µ-sensors based on MEMS technology • fabrication process • with integrated signal processing circuits • µ-scale transfer theory of µ-nano electronic devices • µ-scale heat transfer in MEMS and ICs • High temperature and high frequency MOSFET • Photo - electronic devices and biochips  Researches are complementary to the R&D of IPHC • DUT will install a submicron (0.25µm) CMOS production line in 2008 • First submicron fabrication line in chinese universities IPHC-DUT christine.hu@ires.in2p3.fr

12. R&D Collaboration with DUT Since 2006 • CMOS Sensor Thinning Program: • Thinning down individually CMOS sensors designed by IPHC to 30 - 40 µm • Experiences in fabrication of ultra thin thermal & pressure MEMS • Equipments: ex. ALCATEL dry etching machine • R&D of Integrated Signal Processing Architecture: • Optimization of mixed µ-circuits, e.g. ADC • Educational Program: • IPHC has provided a microelectronic (circuit design) training course to DUT's Master and PhD students • Signed in Spring 2007: collaboration agreement between DUT and ULP • Help academic exchanges IPHC-DUT christine.hu@ires.in2p3.fr

13. R&D Program with DUT for 2008 and future • CMOS sensor thinning and micro interconnection between chips: • They are necessary steps for 3D integration • Optimal fabrication process Studies: • Possibility to optimize EPI layer thickness & doping parameter (from Sept. 2008) • Transfer pixel design know-how to DUT • Integrated signal processing architecture R&D: • Optimization of mixed µ-circuits • Educational program: • IPHC provides every year a microelectronic training course to DUT's Master and PhD students • Welcome microelectronic PhD students • with Franco-Chinese supervision IPHC-DUT christine.hu@ires.in2p3.fr

14. Conclusion • Preliminary results of this collaboration shows that IPHC & DUT are complementary • DUT is one of our important partner for 3DIT • "LIA" framework is also very important to foster academic exchanges among fundamental research and advanced technological research IPHC-DUT christine.hu@ires.in2p3.fr