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Seoul National University

Seoul National University. Introduction. Seoul National University. Why do you want to study Computer Architecture?. Because….You won’t graduate if you don’t take this course. Because….You want to design the next great instruction set.

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Seoul National University

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  1. Seoul National University Introduction

  2. Seoul National University Why do you want to study Computer Architecture? • Because….You won’t graduate if you don’t take this course. • Because….You want to design the next great instruction set. • Instruction set architecture has largely converged, especially in the desktop/server/laptop space. • Dictated by powerful market forces (Intel/ARM). • Because….You want to become a computer architect and design the next great computer systems. • Because….The design, analysis, implementation concepts that you will learn are vital to all aspects of computer science and engineering – operating systems, computer networks, compiler, programming languages • Because….The course will equip you with an intellectual toolbox for dealing with a host of systems design challenges From Prof. Fernando C. Colon Osorio’s lecture notes

  3. Seoul National University Course Goals • To understand • Interfaces • Instruction Set Architecture (ISA) – The Hardware/Software Interface • Engineering methodology / Correctness criteria / Evaluation methods / Technology trends involved in • Processor • Cache memory • Virtual memory • I/O system

  4. Seoul National University Interface Source : http://www.webster.com

  5. Seoul National University Abstract Data Type (ADT) as an Example of Interface • Abstract data type : A set of data values (state) and associated operations that are precisely specified independent of any particular implementation • ADT Example : stack push pop (top) Create_stack Destroy_stack ·· (bottom) stack S is_empty

  6. Seoul National University Abstract Data Type (ADT) as an Example of Interface • Operations viewed as state transformation 4 Push (s, 4) 5 5 1 1 2 2 S S` (After) stack (Before) stack

  7. Seoul National University Abstraction • Before After Jeff Kramer, “Is Abstraction the Key to Computing,” Communications of ACM, April 2007, Vol. 50, No. 4, pp. 37 - 42.

  8. Seoul National University Abstraction • Before After

  9. Seoul National University Abstraction • Before After JinwookSeo, “Information Visualization Design for Map Use on Future Mobile Devices (Presentation at Samsung Electronics, Dec. 8, 2008)

  10. Seoul National University Instruction Set Architecture (ISA) Application Operating System library S/W complier assembler ISA H/W

  11. Seoul National University Instruction Set Architecture as an ADT • “…the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.” - Amdahl, Blaauw, and Brooks, 1964

  12. Seoul National University 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 12 12 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 1 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 21 20 ·· ·· 3 3 7 7 2 2 2 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers add r1, r2, r3 Before Register and Memory After Register and Memory

  13. Seoul National University 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beqr0, r1, 2) 8 8 23 23 r2 r2 12 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 21 22 ·· ·· 3 3 7 7 2 2 2 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers lw r2, 1(r0) Before Register and Memory After Register and Memory

  14. Seoul National University 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 22 23 ·· ·· 3 3 7 7 2 2 8 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers sw r3, 0(r0) Before Register and Memory After Register and Memory

  15. Seoul National University 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 23 24 ·· ·· 3 3 7 7 2 2 8 8 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers beq r0, r1, 2 Before Register and Memory After Register and Memory

  16. Seoul National University 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 0 0 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 24 15 ·· ·· 3 3 7 7 2 2 8 8 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers j 15 Before Register and Memory After Register and Memory

  17. Seoul National University Design Techniques • For Each Design Technique • Engineering methodology • Correctness criteria • Evaluation methods • Technology trends

  18. Seoul National University Design Techniques Sequential implementation Pipelined implementation Out of order execution Speculative execution Processor Processor I-cache D-cache Cache Memory Unified cache Memory Hierarchy To main memory / I/O Systems Virtual Memory Input/Output and Storage

  19. Seoul National University Engineering methodology • Rule 1 : Identify and optimize the common case • Rule 2 : Make the rare case correct and reasonably fast

  20. Seoul National University Correctness criteria • Examples • Pipelined execution : pipelined execution of instructions is correct if the results is as if the instructions were executed sequentially • Cache memory : execution of instructions on a system with cache memory is correct if the results is as if the instructions were executed on the same system but without cache memory • We’ll see a lot of as if’s

  21. Seoul National University Performance Evaluation Methods • Performance types • Time • response time • execution time • Rate • throughput : MIPS, MFLOPS • bandwidth : Mbps • Ratio • relative performance (both time and rate)

  22. Seoul National University Technology Trends • Transistors Per Die Trends • Processor Performance Trends • Processor Computations/Energy Trends • Processor Clock Rate/Power Trends • DRAM Technology Trends • Hard Disk Drive (HDD) Technology Trends • Flash Memory Technology Trends

  23. Seoul National University Transistors Per Die Trends Source: www.icknowledge.com

  24. Seoul National University Processor Performance Trends David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009.

  25. Seoul National University Processor Computations/Energy Trends J. G. Koomey, et al. “Outperforming Moore’s Law” IEEE Spectrum, Vol. 47, No. 3, Mar. 2010, pp. 68 – 68.

  26. Seoul National University Processor Clock Rate/Power Trends David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009. S. H. Fuller and L. I. Millett. “Computing Performance: Game Over or Next Level” IEEE Computer, Vol. 44, No. 1, Jan. 2011, pp. 31 – 38.

  27. Seoul National University DRAM Technology Trends year size cycle time 1980 64 Kbits 250 ns 1983 256 Kbits 220 ns 1986 1 Mbits 190 ns 1989 4 Mbits 165 ns 1992 16 Mbits 145 ns 1996 64 Mbits 125 ns 2000 256 Mbits 100 ns (4x in fouryears) (4x in three years) 60% increase/year David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009.

  28. Seoul National University Hard Disk Drive (HDD) Technology Trends E. Grochowski and R. E. Fontana, Jr., “An Analysis of Flash and HDD Technology Trends,” Flash Memory Summit 2011. Disk density: 1.50x - 1.60x per year (4x in three years)

  29. Seoul National University Flash Memory Technology Trends S. Deutsch, “Bringing Solid State Drives to Mainstream Notebooks,” Flash Memory Summit 2007. P. Ranganathan. “From Microprocessors to Nanostores: Rethinking Data-Centric Systems,” IEEE Computer, Vol. 44, No. 1, Jan. 2011, pp. 39 – 48.

  30. Seoul National University Pitfalls of Computer Technology Forecasting • DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.” Microsoft, 1980 • “640K ought to be enough for anybody.” Bill Gates, 1981 • “Computers in the future may weigh no more than 1.5 tons.” Popular Mechanics • “I think there is a world market for maybe five computers.” Thomas Watson, IBM Chairman, 1943 • “There is no reason anyone would want a computer in their home.” Ken Olsen, DEC founder, 1977 • “The 32-bit machine would be an overkill for a personal computer.” Sol Libes, ByteLines From Prof. BehroozParhami’s lecture notes

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