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Center for Embedded Computer Systems University of California, Irvine

SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations. Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu/~spark. Supported by Semiconductor Research Corporation. M e m o r y. x = a + b c = a < b. If Node. c.

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Center for Embedded Computer Systems University of California, Irvine

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  1. SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu/~spark Supported by Semiconductor Research Corporation

  2. M e m o r y x = a + b c = a < b If Node c T F Control d = e - f g = h + i ALU Data path j = d x g l = e + x High Level Synthesis Transform behavioral descriptions to RTL/gate level From C to CDFG to Architecture x = a + b; c = a < b; if (c) then d = e – f; else g = h + i; j = d x g; l = e + x;

  3. Focus of this Paper • Spark High-Level Synthesis Framework • Comprehensive synthesis framework • Coordinated Coarse & Fine-Grain HLS and Compiler optimizations • C Input => RTL VHDL Output • Results in terms of Logic Synthesis Results (Area/Timing) • Large, real-life applications: MPEG, Image Processing • Descriptions with complex and nested conditionals and loops • Objectives: • Improve quality of HLS results by extracting a high degree of parallelization • Reduce impact of control constructs on QOR • Improve controllability of the HLS solutions

  4. Recent Related Work • Code motions in the presence of conditionals • Condition Vector List Scheduling [Wakabayashi 89] • Path Based Scheduling [Camposano 91] • Symbolic Scheduling [Radivojevic 96] • WaveSched Scheduler [Lakshminarayana 98] • Basic Block Control Graph Scheduling [Santos 99] • Early work was on data-intensive DSP algorithms • Pipelining, Algorithmic transformations

  5. SPARK High Level Synthesis Framework • C Input => RTL VHDL Output • VHDL => Logic Synthesis Results • Customizable Scheduler • Modular toolbox of transformations • Heuristics select transformations

  6. The Intermediate Representation • Spark uses Hierarchical Task Graphs (HTG) • Consists of hierarchy of basic blocks and HTG nodes • 3 Types of HTG Nodes: Single, Compound, Loop • Enables application of coarse and fine grain optimizations • Can regenerate C code • Augmented by data dependency graphs

  7. Loop HTG Node

  8. Trailblazing: Code Motion Technique • HTGs enable Hierarchical Operation Moves • Does not visit each node in the graph

  9. Across HTG Across HTG + Speculate Speculate Across HTG Scheduling Heuristic BB 0 a • Get Available Ops • a, b, c, d • Determine Code Motions Required • Assign Cost to each Operation • Cost is based on data dependency chain • Schedule Op with lowest Cost + BB 1 b + BB 2 BB 3 BB 4 BB 5 c + BB 6 BB 7 BB 8 BB 9 + d

  10. Across HTG BB 0 a + c + + BB 1 + d d b + + + BB 2 BB 3 Conditional Speculation BB 4 BB 5 Speculate BB 6 BB 7 BB 8 Across HTG BB 9 + d Scheduling Heuristic BB 0 a + BB 1 b + BB 2 BB 3 BB 4 BB 5 c + BB 6 BB 7 BB 8 BB 9 + d

  11. Experimentation • Experiments for several transformations • Speculative Code Motions • Transformations applied during scheduling: Dynamic CSE • We have used Spark to synthesize designs derived from several industrial designs • MPEG-1 Prediction Block • GIMP Image Processing software • Scheduling Results • Number of States in FSM • Cycles on Longest Path through Design • VHDL: Logic Synthesis • Critical Path Length (ns) • Unit Area

  12. Speculative Code Motions 50 % reduction in delay with 20 % Area increase Code Motions: Logic Synthesis Results Within Basic Blocks & Across Hierar. Blocks + Reverse Speculation & Early Condition Execution + Speculation Condition Speculation

  13. Speculative Code Motions + Dynamic CSE 75 % reduction in delay with No Area increase Dynamic CSE 30 % reduction in delay, 25 % reduction in Area CSE/Dynamic CSE Results All Code Motions Enabled + Only Dyanmic CSE + Only CSE + CSE & Dynamic CSE

  14. Conclusions • Comprehensive High-Level Synthesis framework • Behavioral C to RTL VHDL • Hierarchical IR + Parallelizing Transformations • Toolbox of Transformations guided by Heuristics • Basic compiler transformations: CSE, Copy Propagation • Platform for applying Coarse and Fine-grain Optimizations • Experimentation with large industrial applications

  15. Thank You

  16. Additional Slides

  17. Eliminating Dependencies by Renaming

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