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Test of Link and Control Boards with LHC like beam, CERN, May 2003

Test of Link and Control Boards with LHC like beam, CERN, May 2003. Karol Bunkowski Warsaw University. Tested functionalities of Link System. S ynchronization of signal s from chamber s H istogram of signals in synchronization window Histogram of all signals from chambers

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Test of Link and Control Boards with LHC like beam, CERN, May 2003

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  1. Test of Link and Control Boards with LHC like beam, CERN, May 2003 Karol Bunkowski Warsaw University Karol Bunkowski, Warsaw University

  2. Tested functionalities of Link System • Synchronization of signals from chambers • Histogram of signals in synchronization window • Histogram of all signals from chambers • Histogram “bx history” • “Snapshots” • Test pulses • TTCrx signals distribution • LB FPGAs loading from CB • CCU and VME interfaces Karol Bunkowski, Warsaw University

  3. Test PulsesSharpness of the Synchronization Window Test pulse directly connected to input channel with short (~5cm) cable Test pulse Synchronization window widow open widow close The sharpness of the synchronization window edge is ~0.3 ns (one channel) Karol Bunkowski, Warsaw University

  4. Test PulsesInput Channels Skew One test pulse directly connected to each input channel Found problem: big skew between input channels (~1ns) Reason: differences in paths lengths on the PCB After fixing the paths lengths the skew should be reduced to ~0.4ns Karol Bunkowski, Warsaw University

  5. Beam testsHistograms The muon beam profile The „bx history” histogram - train of 48 bx’s with muons Karol Bunkowski, Warsaw University

  6. Beam testsWindow Size and Position Scans Ratio of chamber noise signals in synchronization window to all measured. The beam bunch time shape scanned with 1ns window Karol Bunkowski, Warsaw University

  7. Beam testsSnapshots Bx RB1 Channel RB2 Karol Bunkowski, Warsaw University

  8. Beam testsSnapshots, Clusters Size Distribution Karol Bunkowski, Warsaw University

  9. Conclusions The histograms and snapshots work well and have proved their usefulness in testing the performance of chambers. TTCrx signals distribution, test pulses and FPGA loading work well. It should be possible to reduce the skew of input channels and output of test pulses by fixing the paths lengths on a LB PCB Optical link will be tested as soon as the quartz for the PLL is available Problems with CCU block transfer and I2C control of FEBs Karol Bunkowski, Warsaw University

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