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COMP211 Computer Logic Design Lecture 6. Digital Building Blocks #6 Memory

COMP211 Computer Logic Design Lecture 6. Digital Building Blocks #6 Memory. Prof. Taeweon Suh Computer Science Education Korea University. Memory. Digital systems including computer systems require memories to store data Registers (made from flip-flops) are kind of memory

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COMP211 Computer Logic Design Lecture 6. Digital Building Blocks #6 Memory

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  1. COMP211Computer Logic DesignLecture 6. Digital Building Blocks #6 Memory Prof. Taeweon Suh Computer Science Education Korea University

  2. Memory Digital systems including computer systems require memories to store data Registers (made from flip-flops) are kind of memory • But, how many transistors need to build a 1-bit register (that is, memory to store 1-bit) with a flip-flop? Here we study memory arrays that can efficiently store large amounts of data • RAM and ROM

  3. Memory Random Access Memory (RAM) • Static Random Access Memory (SRAM) • Data stored so long as power is applied • 6-transistors per cell • Faster • Differential • Dynamic Random Access Memory (DRAM) • Require periodic refresh • Smaller (can be implemented with 1 or 3 transistor) • Slower • Single-Ended • Can be read and written Read-Only Memory (ROM) Modified from Prof H.H.Lee’s slide, Georgia Tech

  4. Example DDR SDRAM (Double Data Rate Synchronous DRAM) • Widely being used for main memory in computers

  5. Read/Write Block Diagram of Memory N-bit address lines Memory • Example: Byte-addressable 2MB memory • M = 8 (because of byte-addressability) • N = 21 (1 word = 8-bit) N 2N words (M-bit per word) Chip Enable M M-bit Data Output (for Read/Write) An M-bit data value can be read or written at each unique N-bit address. Modified from Prof H.H.Lee’s slide, Georgia Tech

  6. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Memory Organization Example 4 words x 8 bits Wordline (WL) 2-to-4 Decoder 0 A0 1 2 A1 3 CS Chip Select BitLine D6 D4 D2 D0 D7 D5 D3 D1 Modified from Prof H.H.Lee’s slide, Georgia Tech

  7. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit How to Address Memory 4 words x 8 bits 2-to-4 Decoder 0 A0=1 1 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 A1=0 3 CS Chip Select=1 D6 D4 D2 D0 D7 D5 D3 D1 Access address = 0x1 Modified from Prof H.H.Lee’s slide, Georgia Tech

  8. BitLine Static Random Access Memory (SRAM) Wordline (WL) BitLine Typically each bit is implemented with 6 transistors (6T) Read operation • The bitline and its inverse are precharged to Vdd (1) • Then set Wordline (WL) high • Depending on the value stored, either bitline or ~bitline goes low Write operation • Put the new value on Bitline and its inverse on ~Bitline • Then set the Wordline to high Modified from Prof H.H.Lee’s slide, Georgia Tech

  9. Dynamic Random Access Memory (DRAM) Wordline (WL) Bitline 1-transistor DRAM cell Write operation • Put value on bitline and then set WL=1 Read operation • Prechargebitline to Vdd (1) • Assert WL to 1 Storage decays, thus requires periodic refreshing • Read bitline data and write again to keep the value in the memory cell Modified from Prof H.H.Lee’s slide, Georgia Tech

  10. Memory Description Capacity of a memory is described as • # addresses x Word size • Examples: Slide from Prof H.H.Lee, Georgia Tech

  11. Example

  12. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Memory with 2 Decoders 8 words x 4 bits 2-to-4 Decoder Row Decoder 0 A1 1 2 A2 3 CS Tristate Buffer (read) D0 D1 D2 D3 0 1 Chip Select CS 1-to-2 Decoder Column Decoder A0 Modified from Prof H.H.Lee’s slide, Georgia Tech 12

  13. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 0 Read Operation 8 words x 4 bits 0 A1 1 2-to-4 Row Decoder 2 A2 3 CS D0 D1 D2 D3 0 1 Chip Select CS 1-to-2 Column Decoder Modified from Prof H.H.Lee’s slide, Georgia Tech A0 = 0

  14. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 1 Write Operation 8 words x 4 bits Memory 0 A1 1 2-to-4 Row Decoder 2 A2 3 CS D0 D1 D2 D3 0 1 Chip Select CS 1-to-2 Column Decoder Slide from Prof H.H.Lee, Georgia Tech A0 = 1

  15. D7 D6 D5 D4 A19 A19 1Mx4 1Mx4 D3 A18 A18 A17 A17 D2 D1 D0 A0 A0 R/W R/W CS CS CS Building Memory in Hierarchy Design a 1Mx8 using 1Mx4 memory chips Slide from Prof H.H.Lee, Georgia Tech

  16. D3 D2 D1 D0 1-to-2 Decoder 1 A20 0 A19 A19 1Mx4 1Mx4 A18 A18 A17 A17 CS A0 A0 R/W R/W CS CS Building Memory in Hierarchy • Design a 2Mx4 using 1Mx4 memory chips Note that 1-to-2 decoder is the wire itself (or use an inverter) Slide from Prof H.H.Lee, Georgia Tech

  17. A19 D7 A18 A19 A19 A19 A19 1Mx4 1Mx4 1Mx4 1Mx4 A18 A18 A18 A18 D6 A17 A17 A17 A17 A17 D5 D4 A0 CS CS CS CS R/W R/W R/W R/W A0 A0 A0 A0 D3 1-to-2 Decoder 1 D2 D1 0 D0 A20 CS Building Memory in Hierarchy • Design a 2Mx8 using 1Mx4 memory chips Slide from Prof H.H.Lee, Georgia Tech

  18. HDL Representation of RAM `timescale 1ns / 1ns module ram_tb(); reg clk; reg we; reg [7:0] addr; reg [31:0] din; wire [31:0] dout; parameter clk_period = 10; ram ram_uut(clk, we, addr, din, dout); always begin clk = 1; forever #(clk_period/2) clk = ~clk; end initial begin addr = 4'h00; we = 1'b0; din = 32'h00000000; #3; addr = 4'h00; we = 1'b1; din = 32'h00001111; #(clk_period*1); addr = 4'h02; we = 1'b1; din = 32'h22223333; #(clk_period*1); addr = 4'h09; we = 1'b1; din = 32'h9999AAAA; #(clk_period*1); addr = 4'h34; we = 1'b1; din = 32'h34343434; #(clk_period*1); we = 1'b0; #(clk_period*1); addr = 4'h09; #(clk_period*1); addr = 4'h02; #(clk_period*1); addr = 4'h34; #(clk_period*1); addr = 4'h00; #(clk_period*1); end endmodule module ram #(parameter N = 8, M = 32) (input clk, input we, input [N-1:0] adr, input [M-1:0] din, output [M-1:0] dout); reg [M-1:0] mem[2**N-1:0]; always @(posedge clk) if (we) mem[adr] <= din; assign dout = mem[adr]; endmodule RAM (synchronous with clock)

  19. Read Only Memory (ROM) ROM K-bit address lines N-bit Data Output 2k words (N-bit per word) K N “Permanent” binary information is stored Non-volatile memory • Power off does not erase information stored Slide from Prof H.H.Lee, Georgia Tech

  20. 32 x 8 (32 words x 8 bits) ROM 32x8 ROM 5 8 Each represents 32 wires 0 A4 1 2 A3 5-to-32 Decoder 3 A2 A1 28 29 A0 30 31 D1 D0 D7 D6 D5 D4 D3 D2 Slide from Prof H.H.Lee, Georgia Tech

  21. 0 A4 1 2 A3 5-to-32 Decoder A2 A1 29 A0 30 31 D0 D1 D7 D6 D5 D4 D3 D2 Programming the 32x8 ROM Slide from Prof H.H.Lee, Georgia Tech

  22. HDL Representation of ROM module rom(input [1:0] adr, output reg [2:0] dout); always @(adr) case(adr) 2'b00: dout <= 3'b011; 2'b01: dout <= 3'b110; 2'b10: dout <= 3'b100; 2'b11: dout <= 3'b010; endcase endmodule 4 X 3 (4 words x 3 bits) ROM

  23. Other Flavors of ROMs Reprogrammable ROMs • EPROM (Erasable Programmable ROM) • Use UV (Ultra Violet) light for erasing • EEPROM (Electrically Erasable Programmable ROM) Flash memory • Read and Writable • Non-volatile • Power off does not erase information stored Modern ROMs are not really read only • They can be reprogrammed as well Flash memory has become extremely popular to store large amounts of data in portable systems such as cameras and music players

  24. Programmable Logic Array (PLA) Programmable OR Plane A B C Programmable AND Plane C C B B A A F1 F2 PLA implement two-level combinational logic in SOP form Concept of PLA is used in the decoding stage of CPU design Older technology Modified from Prof H.H.Lee’s slide, Georgia Tech

  25. AC BC A B C Example using PLA A B C AB C C B B A A Modified from Prof H.H.Lee’s slide, Georgia Tech F2 F1

  26. FPGA Field Programmable Gate Array (FPGA) can implement both combinational and sequential logic • PLA can implement only combinational logic Using CAD tools, a user can implement designs on the FPGA using either an HDL or a schematic It is programmable in the “field” • FPGA is reprogrammable (reconfigurable) after a system is deployed 2 Major FPGA companies • Xilinx: www.xilinx.com • Altera: www.altera.com

  27. FPGA Examples

  28. That’s it! Folks I hope you have enjoyed this class You just got one step further to understand the computer See you next semester in the computer architecture class

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