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1. Digital Design: Combinational Logic Blocks
2. 2 Multiplexers (Data Selectors) A multiplexer (MUX for short) is a digital switch:
it passes (connects) one of its data inputs to the output.
the data input selected is a function of a set of control inputs called selection inputs.
3. 3 Multiplexers (contd)
4. 4 Gate level implementation of muxes 2:1 mux
4:1 mux
5. 5 Cascading multiplexers Large multiplexers can be made by cascading smaller ones
6. 6 Multiplexers as general-purpose logic A 2n:1 multiplexer can implement any function of n variables
with the variables used as control inputs and
the data inputs tied to 0 or 1
Example:
F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC
7. 7 Multiplexers as general-purpose logic (contd)
8. 8 Activity Realize F = BCD + ABC with a 4:1 multiplexer
9. 9 Multiplexer with bus inputs and outputs
10. 10 Demultiplexers Route a single input to one of many outputs, as a function of a set of control inputs
11. 11 Three-State Buffers Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other (multiple drivers conflict).
Use of tri-state logic permits the outputs of two or more gates or other logic devices to be connected together
12. 12 Tri-state Buffers (contd)
13. 13 Tri-state Buffers application examples
14. 14 Tri-state Buffers application examples (contd)
15. 15 Tri-state buffers application examples (contd)
16. 16 Tri-state Buffers application examples (contd)
17. 17 Decoders A decoder is a logic circuit that converts coded inputs into coded outputs.
Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs)
18. 18 Decoders (contd)
19. 19 Binary Decoders The most common decoder circuit is an n-to-2n decoder (or binary decoder)
20. 20 Binary Decoders (contd)
21. 21 Binary Decoders (contd)
22. 22 Gate level implementation of decoders
1:2 decoders
2:4 decoders
23. 23 Decoders as general-purpose logic n-to-2n decoders can implement any function of n variables
with the variables used as control inputs
the appropriate minterms summed to form the function
24. 24 Decoders as general-purpose logic (contd) F1 = A'BC'D + A'B'CD + ABCD
F2 = ABC'D' + ABC
F3 = (A' + B' + C' + D')
25. 25 Encoders An encoder performs the inverse function as a decoder
The simplest encoder to build is a 2n-to-n (binary encoder)
26. 26 Priority Encoders
27. 27 Priority Encoders (contd)
28. 28 Programmable Arrays ROM (read only memories)
PLA (programmable logic array)
PAL (programmable array logic)
CPLD (complex programmable logic devices)
FPGA (field programmable gate arrays)
29. 29 Read-Only Memories (ROM) A ROM consists of a two dimensional array of semiconductor devices interconnected to store an array of binary data
Two-level canonical form combinational logic can be implemented using a ROM as a look-up-table (LUT)
30. 30 Combinational logic using a ROM
31. 31 ROM Structure
32. 32 PLA (Programmable Logic Arrays) A PLA performs the same basic LUT task as a ROM.
A PLA with n inputs and m outputs can realize m combinational functions of n variables.
The internal organization of a PLA is different from that of the ROM
33. 33 PLA (contd)
34. 34 PLA short-hand notation
35. 35 Activity Map the following functions to the PLA below:
W = AB + AC + BC
X = ABC + AB + AB
Y = ABC + BC + BC
36. 36 Activity (contd) 9 terms wont fit in a 7 term PLA
can apply concensus theorem to W to simplify to: W = AB + AC
8 terms wont fit in a 7 term PLA
observe that AB = ABC + ABC
can rewrite W to reuse terms: W = ABC + ABC + AC
Now it fits
W = ABC + ABC + AC
X = ABC + AB + AB
Y = ABC + BC + BC
37. 37 PAL (Programmable Array Logic) The PAL is a special case of the PLA in which the AND array is programmable and the OR array is fixed
38. 38 Implementation of a Full Adder Using a PAL
39. 39 CPLDs and FPGAs The distinction between CPLD and FPGAs is blurred.
40. 40 Example of CPLD Internal Structure
41. 41 Example of FPGA Internal Structure
