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Front-end readout study for SuperKEKB

Front-end readout study for SuperKEKB. IGARASHI Youichi. Requirements of Front-end from DAQ. Trigger decision time (3 m sec ~ 6 m sec) Buffer size of L1 Trigger : 6 m sec Rapid trigger communication Trigger/Busy handshake Event Tag.(ID?) receiving

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Front-end readout study for SuperKEKB

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  1. Front-end readout study for SuperKEKB IGARASHI Youichi

  2. Requirements of Front-end from DAQ • Trigger decision time (3msec ~ 6msec) • Buffer size of L1 Trigger : 6 msec • Rapid trigger communication • Trigger/Busy handshake • Event Tag.(ID?) receiving • Dead-time must be less than a few msec • Data transport to DAQ system • (Trigger pattern information transport to GDL)

  3. Unification idea by DAQ group TRIGGER • Unification point • Behind L1 FIFO and data link unification • The Link(RocketIO) for Data transfer is chosen. • RX/TX on COPPER board. TT-SW New timing Distributor Control TX/RX FINESSE Detector FE, A/D L1FIFO Unified TX/RX COPPER Xilinx RocketIO Detector FE, A/D Detector FE, A/D TT-RX FPGA FE board

  4. Detectors and readout methods

  5. SVD front-end • APV-25 readout baseline designworks already. • SVD group will progress to w/o FADC crate design to reduce module space and power consumption. Now

  6. PID front-end HAPD • Aerogel RICH • HAPD + SA system works. • The hit-pattern digital transfer by UNIFIED interface is checked up. • TOP ? FPGA SA (ASIC) DAQ UNIFIED interface HAPD SA (ASIC) HAPD SA (ASIC) HAPD SA (ASIC)

  7. ECL front-end • COPPER based Waveform digitizer was tested. • VME U9 Shaper ADC Waveform Analyzer is planed.

  8. KLM front-end • RPC : • time-multiplex COPPER TDC system works. • The hit-pattern digital transfer by UNIFIED interface is checked up. • New Scintillator : • The hit-pattern digital transfer by UNIFIED interface ?

  9. G.S.Varner’s Proposal • Waveform sampling for all detectors • TARGET : • 1GHz, 9bit digitizer • BLAB2 : • 10GHz digitizer which can be used high-resolution time measurements

  10. CDC Readout study with DAQ UNIFIED interface • CDC FE prototype card • A study about CDAQ/Front-end data transport. • A study about GDL/Front-end data transport • A study of the CDC readout scheme • Charge measurements by (slow) FADC • Drift time measurements by FPGA based TDC • A study of common mode noise from the front-end readout board to CDC • Aconfirmation of front-end specification • G.V.’s proposal FE will be tested in parallel.

  11. CDC FE Prototype card Under 20cm • 16ch/board • BJT-ASB/Discriminator • FADC: over 20MHz / 10bit • FPGA : Vertex-5 LXT • TDC: 1 nsec counting • FADC reading • Control • FPGA: Spertan3A • SiTCP for CDC study • Connectors • RJ-45 for SiTCP • RJ-45 for DAQ timing signals • RJ-45 for DAQ data line • SFP for DAQ data line • Optical TX/RX for GDL • LEMO input x 3, output x1 • Shielded substrate RJ45 RJ45 ASB + Discriminator Optical Transceiver SFP Optical Transceiver FADC ASB + Discriminator FPGA (CONTROL, TDC) ASB + Discriminator FADC FPGA (SiTCP) ASB + Discriminator RJ45

  12. Front-end(for system test) ASB Amp. Shaper Buffer 4ch/chip Peaking time ~４０nsec Gain : -360mV/pC ~ -1400mV/pC (4 step variable) Disc. ASB D-out protection A-out Fe source

  13. TDC in FPGA Input： Hoshin 16bit TDC tester • To use 4 different phase 250MHz Clock in the aim of 1 nsec counting Latch each clock timings RMS=0.51ns 0 0 1 1 Encode latched pattern 4ns

  14. CLK For GFP LOGIC part diagram LVDS 2 pairs RocketIO GFP Optical connector LVDS 2 pairs RocketIO GFP SFP (Optical connector) CONTROL 3x4 16 ASB Discriminator TDC (with FIFO) TIMING LVDS 4x4 pairs RocketIO GFP LVDS 2 pairs RJ-45 LVDS 8 pairs FADC Ti ADS5287 5 FIFO LVDS 4 pairs RJ-45 16 De-serializer Spertan3A SiTCP CLK 50MHz ASB Discriminator 15 100base PHY RJ-45 LVDS CLKs 48 8 TEST PIN CONTROL 32 DIP-SW ASB Discriminator LVDS 8 pairs FADC Ti ADS5287 PUSH SW Vertex-5 LXT (XC5VLX50T, IO:360pin) 3 5 LEMO 4 LEMO LVDS CLKs LED ASB Discriminator 8 LEMO DIP-SW 16 LEMO TEST PIN 8 Sampling CLK 20~40 MHz CLK 125MHz CLK 42.33MHz DAC (Vth)

  15. Scheduled plan

  16. Summary • Each detector groups are progressing to design the detector Front-end. • G.V. offer good two high speed waveform samplers to unified FE. • The unification by the waveform sampler should be discussed. • Those prototype is available. • UNIFIED interface R&D has been started in collaboration with CDC group. • Issues • Treatments about over 20 MB/sec/link speed data flow • COPPER can treat up to 40MB/sec data flow w/o network. • Will detector groups request more faster single link data flow ? • Discussion with the groups which thinking COPPER-less option.

  17. Backups

  18. SVD front-end

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