Variation Aware Placement in FPGAs

1. Variation Aware Placement in FPGAs Suresh Srinivasan and Vijaykrishnan Narayanan Pennsylvania State University, University Park

2. Cout Interconnect Switch Matrix Logic Slice Logic Slice Clock I0 Local Feedback Logic Slice Logic Slice Cin CLB CLB Multiplier Introduction • Field Programmable Arrays(FPGA) are becoming popular due to their short-design times and cost-effectiveness. • Increasing popularity and demands compelling to move to sub-100nm domain.

3. Problems in sub-100nm domain • Unpredictability in the process parameters, “PROCESS VARIATIONS” • Variations in devices’ gate length, threshold voltages, oxide thickness etc. • Thereby variations in the power and performance of devices. • Drastic impacts of such variations demonstrated on FPGAs*: • Leakage Power increase by 2X. • 3X increase in the delay of the LUTs. • Manufacturing yield affected  cost for industry • Solutions for such problems in FPGAs • NONE YET – THIS IS THE START!!! *P. Wong, L. Cheng, Y. Lin and L. He, "FPGA Device and Architecture Evaluation Considering Process Variation," Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2005.

4. Observing the impact • The impact on different components • Configuration Bits (SRAM cells) • POWER – SRAM cells used are high Vt • Leakage power: Not significant in total power since its really low. • Dynamic power only once during configuration. • Performance • Not in the critical path, so not an issue • LUT Multiplexer • Both power and performance are an issue • Routing Fabric • Both power and performance are an issue

5. 4x1 Mux SRAM SRAM 4x1 Mux 4x1 Mux 4x1 Mux 4x1 Mux SRAM Impact on LUT MUX Nominal operating threshold 2X leakage power increase LUT MUX Design 1.3X Variation in delay with 20% Vt variations Nominal operating threshold

6. Average increase by 20% Impact on Applications

7. Generate Gaussian Distribution of SLICE Thresholds Obtain delay and leakage of the SLICEs Set a leakage and delay threshold for discarding Generate constraint file ISE tool flow Choose the Last Successful placement If PAR successful N Y Solutions to the problem • Detect power/delay numbers for each SLICE. • Pre configuration of sensors to determine slice delay/power. • Caution while placement. Two placement strategies: • Block Discard Policy (BDP): Discard blocks with delay, power product > Threshold (Set based on utilization of device) • Iterative process as indicated • Variation Aware Placement (VAP): Incorporate variation costs in placement algorithm. B D P

8. Implementation Details • BDP Implementation • Xilinx ISE ver. 6.0. • Used PAR with User Constraint File (UCF), to constrain the placement. • Variation Aware Algorithm (VAA) • Needed change in algorithm  Can’t use Xilinx tools • Open source FPGA place & route tool used  VPR (Versatile Place and Route) • Modified the cost function of the simulated annealing algorithm used by the placer. • Used Xilinx reference designs for benchmarking BDP. • Used MCNC benchmarks for benchmarking VAP.

9. Average 15% savings BDP results * No impact on performance. All designs could meet the required timing

10. Results (VAP)

11. Conclusion • Variation aware placement provides an effective scheme preventing both power and performance related issues in FPGAs due to process variations. • Routing should also be made variation aware. • Detailed impact analysis of such variations in routing fabric needed.