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Techniques and Tradeoffs of Pure-Pin and Multiplexed ICT Architectures

Techniques and Tradeoffs of Pure-Pin and Multiplexed ICT Architectures. May 2006. Alan.Albee@Teradyne.com. Agenda. Multiplexed vs Pure-Pin ICT Architectures Definitions and comparisons Benefits and limitations Dimensions of multiplexing Historical Tradeoffs to Achieve Pure-Pin

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Techniques and Tradeoffs of Pure-Pin and Multiplexed ICT Architectures

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  1. Techniques and Tradeoffs of Pure-Pin and Multiplexed ICT Architectures May 2006 Alan.Albee@Teradyne.com

  2. Agenda • Multiplexed vs Pure-Pin ICT Architectures • Definitions and comparisons • Benefits and limitations • Dimensions of multiplexing • Historical Tradeoffs to Achieve Pure-Pin • Feature limitations • Performance compromises • New Advances in Pure-Pin Design • Pure-pin without performance compromises • Reduced price/performance thresholds

  3. What is Multiplexing? • A technique for sharing (or pooling) tester instruments among a large number of test points • Multiplexing increases the number of test points that have access to ICT instruments • Multiplexing places rules on how test instruments can be accessed during testing IEEE 1149.1

  4. Benefits of Multiplexed ICT Designs • Lower Cost • Fewer instruments required in the ICT system • Higher Performance • Since fewer instruments are required, they can be designed for higher performance • Higher Pincounts • Multiplying effect of multiplexing increases available pincounts • Less Power • Do not need to support infrastructure of instrument behind every test point

  5. Disadvantages of Multiplexed Designs • Programming Restrictions • Limits on which tester nails can be used together • Nail assignment software is required to analyze and resolve conflicts • Fixture Build Delays • Fixture assembler cannot randomly wire nails to test points • Must wait until program and nail assign wiring reports are complete • Real Pin Limitations • High pincount devices may exceed real pin count limits of the multiplexed system • May require tests to be broken up into multiple bursts • Debug Restrictions • Debug activities (like adding guards/isolations) and ECO activities (like adding components) may cause conflicts that require adding or moving fixture wires

  6. Pure-Pin ICT Designs • Designed to Solve Disadvantages Associated with Multiplexed System • Real driver/sensor for every test point • All D/S can be used simultaneously • Less fixture build delays • No real nail limitations • No debug restrictions requiring fixture re-wiring But how can pure-pin systems do this at a reasonable cost?

  7. ICT Pure-Pin Design Compromises • Performance Compromises • Accuracy • Logic level thresholds • Pin logic assignments • Slew rates • Design Compromises • Relay matrix • Backdrive capacity • Driver/sensor flexibility Cost Performance Design and performance tradeoffs are required to make Pure-Pin Systems cost effective…

  8. Design Compromises Result in Program, Fixture, and Debug Limitations Shading indicates potential program, fixture, or debug limitations

  9. Design Compromises Can Limit System Performance & Test Capabilities Performance features are often sacrificed to achieve system cost goals… What are the potential problems with these design compromises?

  10. Problem with Inaccurate Drivers Open loop, high output impedance ICT pins • Blue Waveform: Drive 1.5V with no load • Yellow Waveform: Drive 1.5V into 6Ω load • High Impedance pin only achieves 710mV at DUT Logic switching threshold plus noise margin • Inaccuracy of driver voltage increases as backdrive current increases • Results in false failures under backdrive conditions 3.3V 2.5V 1.2V 0.8V

  11. Value of Accurate Drivers Closed-Loop, Low Impedance Driver Accurate Digital Pin Electronics • Eliminates false failures due to driver inaccuracies • Eliminates incorrect diagnostics in the presence of fault conditions • BlueWaveform: Drive 1.5V with no load • YellowWaveform: Drive 1.5V into 6Ω load • Closed loop, low impedance driver achieves 1.39V at DUT • 110mV error vs 790mV error • 7 times more accurate under loading conditions 5.0V 3.3V 1.2V 0.8V

  12. Problem with Inaccurate Sensors System A System B 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 High Sense Error High Sense Error Logic High Window TRI Error Band Input Voltage (V) at Device Low Sense Error Logic Low Window Low Sense Error ±100mV ±200mV JEDEC 8-14 Wide 0.8V logic level standard, 150mV noise margin

  13. Value of Accurate Sensors UltraPin I Typical 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 Logic High Window High Sense Error Low Sense Error Input Voltage (V) at Device Logic Low Window ±40mV ±15mV JEDEC 8-14 Wide 0.8V logic level standard, 150mV noise margin

  14. Problem with Limited Logic Levels DUT U1IN= 2.4V U2IN = 2.4V U1 U2 1.2V Logic 2.5V Logic Driver B Common VPROG = 2.4V Driver A • Some testers use group or shared logic level assignments • Driver A and B are forced to use the same logic level assignments • Satisfying voltage requirements for U2 causes U1 to be exposed to over-Voltage condition Likely damage to U1 due to violation of VIH max!

  15. Value of Per-Pin Programmable Logic Levels DUT U1IN = 1.1V U2IN = 2.4V U1 U2 1.2V Logic 2.5V Logic VPROG = 1.1V Driver B VPROG = 2.4V Driver A • Each pin’s logic level can be independently programmed • Driver A is programmed to apply 2.4V and Driver B is programmed to apply 1.1V U1 and U2 are tested within their safe operating regions!

  16. Problem with Single Threshold Sensors DUT 0.8V logic device Single Threshold Sensor VDUT = 0.6V JEDEC 8-14 Wide 0.8V logic (JESD8-14) U2 HI = false pass 1.0 0.5 0 Logic “1” VDUT Voltage VTHRESHOLD = 0.4V • Single threshold sensor can easily generate false pass on logic devices • Allows defective product to escape • Single threshold has a problem with ALL logic families including 5V, 3.3V, 2.5V, 1.5V Logic “0”

  17. Value of Dual Threshold Sensors JEDEC 8-14 Wide 0.8V logic (JESD8-14) DUT 0.8V logic device Dual Threshold Sensor 1.0 0.5 0 VHI = 0.7V Hi Threshold Logic “1” Not a logic Hi VDUT VDUT = 0.6V Voltage U2 Not a logic Lo Logic “0” VLO = 0.1V Lo Threshold • Dual threshold sensor identifies incorrect or marginal logic levels on UUT • Prevents defective product from escaping to customer

  18. U2 Problem with Uni-Directional Drivers JEDEC 8-12 1.2V logic VIL (max) is only 420mV DUT Must backdrive U1 low VDUT 1.0 0.5 0 Logic “0” U1 Driver 1.2V logic I = 100mA VDUT + guardband Voltage 1Ω 0V Logic “0” To sensor 100mVerror 200 mVerror • Total driver inaccuracy + guardband is 500mV • Maximum low input for U2 is 420mV • U2 is un-testable, cannot program voltage below 0V to decrease U2 input voltage • Programming driver to -0.2V would fix problem and would still be safe for DUT ±100 mVerror Assumptions: Driver accuracy = ±100mV Driver output resistance = 2Ω Fixture and board resistance = 1Ω Noise guardbanding = 100mV

  19. U2 Value of Accurate Bi-Directional Driver JEDEC 8-12 1.2V logic VIL (max) is only 420mV DUT Must backdrive U1 low VDUT 1.0 0.5 0 Logic “0” U1 VDUT + guardband Driver 1.2V logic I = 100mA Voltage 1Ω 0V To sensor Logic “0” 100mVerror 10 mVerror • Total driver inaccuracy + Noise guard-band is 250mV • Maximum low input for U2 is 420mV • U2 is testable, even without having to change programmed drive voltage to –0.2V, but can adjust to obtain improved noise margin ±40 mVerror Assumptions: Driver accuracy = ±40mV Driver output resistance = 0.1Ω Fixture and board resistance = 0.3Ω Noise Guard-banding = 100mV

  20. U2 Problem with Fixed Slew Rate Drivers DUT VDRIVER U1 90Ω 4ns 65Ω 3ns 45Ω 1.5ns Driver VDUT Pin board pathReceiver pathDUT PCB path • 300V/µs edge rate is too fast for some ICT applications • Transmission line effects will cause overshoot and ringing at the DUT • Cannot lower edge rate to eliminate potentially damaging over-voltage conditions

  21. U2 Value of Programmable Slew Rate Drivers DUT VDRIVER U1 65Ω 3ns 90Ω 4ns 45Ω 1.5ns Driver VDUT Pin board pathReceiver pathDUT PCB path • Fully programmable slew rate will allow user to optimize waveform at the DUT • Transmission line effects can be controlled • Programmable slew rate can eliminate potentially damaging over-voltage conditions

  22. Directly measure and control Backdrive Currents and duration in Real Time, on a per pin basis Value of Real Time Backdrive Current Measurement and Control • Program safe limits for IC devices • Identifies and eliminates excessive backdrive currents that can stress IC components • Identifies faults that are not normally detected • Bad Output Transistors • Open or Faulty Enable Pins • Incorrect Isolation Vectors Debug environment DEVICE LABEL: U33_B1: (NAND tree Test) DEVICE NAME: U33 DEVICE TYPE: 82801 (I/O Controller Hub - 3V) PIN NODE NAIL BACKDRIVE A3 PICH_HLCOMP 106 79.06 mA G1 LAN_RXD1 640 73.79 mA R21 RSMRST_ 90 131.76 mA W11 PCLK_ICH 105 84.33 mA Y20 OVCUR_1 147 469.08 mA R22 FERR 614 76.42 mA C12 CPUINIT_ 743 450.64 mA D11 SB_A20M_ 575 563.95 mA Y17 SUS_STAT 531 73.79 mA GGNT_ 61 171.29 mA RBF_ 67 237.18 mA SBA0 122 176.56 mA Backdrive Failure Device: U33 Type: 82801 Pin: R22 Net: CPUINIT_ Exceeded Backdrive Current Limit of 100 mA Production environment

  23. Problem with Limited System Power • Device packages may have hundreds of Signal pins • Backdrive currents can exceed 250mA or more even on modern devices • Real pin systems allow programmer to drive all pins in parallel • Sum of backdrive currents may exceed limited system power ratings of some systems Result: False failure reports and inaccurate voltages…

  24. Teradyne’s Approach to ICT… Manufacturers shouldn’t have to choose between cost and quality… • Never Compromise Pin Performance • Provide industry’s most accurate Pin • Per pin programmable logic assignments and slew rates • Bi-directional drivers and dual-level sensor thresholds • Real time backdrive current measurement • SafeTest™ protection technologies • 250A system power rating • Make Performance Pins Affordable • Cost-effective, minimally restrictive multiplexed designs • New lower cost UltraPin II pure-pin system Cost Performance Multiplexed Pure-Pin

  25. TestStation is Designed to have the Fewest Multiplexing Restrictions Shading indicates potential program, fixture, or debug limitations Teradyne TS121 provides true non-multiplexed operation ! Teradyne Confidential

  26. UltraPin II: Teradyne’s Next Generation Pin Technology • New UltraPin II 121 Pin Board • Unique, all real, non-multiplexed pin board • 8-wire mux with non-blocking 4-wire analog connections • 128 shelf pins - 128 UltraPin II driver/sensors • Significantly lower per pin pricing than UltraPin I 121 • Uncompromised performance, no feature reduction • Accurately tests down to 0.2V Logic UltraPin II boards are designed to be compatible with UltraPin I test fixtures and test programs !

  27. TestStation is Designed to Feature the Highest Performance ICT Pin TestStation has all the features required to accurately, reliably, and safely perform digital powered-up vector testing!

  28. Pure-Pin vs Multiplexing Summary • There are Many Dimensions to ICT “Multiplexing” • “Pure-Pin” ICT systems may have inherent design limitations • Some multiplexed designs are less restrictive than others • Some Pure-Pin Systems Compromise Performance to Achieve Cost Targets • Accuracy, Logic Levels, Thresholds, Slew Rates, Backdrive Measurement, etc. • High Performance Pins are Required for Testing Modern Technologies • No performance concessions • Accuracy and features of new UltraPin II provides Future-proof ICT solution • Innovative UltraPin II design provides reduced price pure pin option • Pure-Pin or Multiplexed options provide maximum pricing and budget flexibility - without performance compromises! • Common Pin Technologies Provide Easy Migration and Scalability to Fit Changing ICT Requirements

  29. Techniques and Tradeoffs of Pure-Pin and Multiplexed ICT Architectures May 2006 Alan.Albee@Teradyne.com

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