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EMCAL global trigger status: STU design progress

EMCAL global trigger status: STU design progress. Olivier BOURRION LPSC, Grenoble. Overview. Global trigger scheme reminder Technology issue Validation methodology Status Future steps Summary. TTC link. TRU. L0. STU. L1-gamma. To CTP. 34 TRU. LVDS links. L1-jet. DDL.

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EMCAL global trigger status: STU design progress

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  1. EMCAL global trigger status: STU design progress Olivier BOURRION LPSC, Grenoble Alice EMCAL Meeting, July 2nd 2007

  2. Overview • Global trigger scheme reminder • Technology issue • Validation methodology • Status • Future steps • Summary Alice EMCAL Meeting, July 2nd 2007

  3. TTC link TRU L0 STU L1-gamma To CTP 34 TRU LVDS links L1-jet DDL 4 diff pair Ethernet CAT7 cable TRU DCS Put trigger data in the data stream on L2a (via DDL) TRU is clocked by the BC clock forwarded by STU (40.08MHz) Multiplicity from V0 Position of the Summary Trigger Unit in the global trigger scheme Trigger specification : • L0 trigger : OR of the 34 L0 calculated by the TRU. • L1-gamma trigger: Energy summed over sliding window of 4x4 towers (2x2 fast OR) and compared to a multiplicity corrected threshold. • L1-jet trigger : Energy summed over a sliding window of n*n subregions and compared to a multiplicity corrected threshold (a subregion is defined as 8x8 towers) Alice EMCAL Meeting, July 2nd 2007

  4. The technology issue • The feasibility of a LVDS link (TRUSTU) working at 2*400.8 Mbs over 15m has to be checked. (see Frascati presentation) • The STU design and fabrication on hold  waiting for this validation. Alice EMCAL Meeting, July 2nd 2007

  5. USB LVDS Validation methodology • An emitting buffer is loaded via the testing tools • A frame transfer is initiated • The receiving buffer is read by the testing tools Above steps have to be repeated many times with different packet contents. This scheme is exercising the link as in the final design. It also debugs the serial protocol (local and global trigger side). Testing tools CAT7 LVDS cable 15m Slow control LVDS Trigger OR USB developed for PHOS by the university of Bergen Alice EMCAL Meeting, July 2nd 2007

  6. Status on this issue Reminder: the original calendar was to do this testing before summer 2007 • Develop the serializer/deserializer VHDL code (with automated frame and character alignment) Done! • Develop and validate the testing tools (hardware and software)  Done! • Validate the link speed feasibility with a loopback test  The test scheduling will depend on the availability of the TOR board Alice EMCAL Meeting, July 2nd 2007

  7. Future steps • Design and built the first STU prototype (on hold) • Implement a global L1-(could be validated with 2 TRU).This step could also be done with a TOR. • Implement a first version of a L1-jet • Implement and test the DDL interface(LPSC is about to be equipped with a Acquisition computer running DATE) • Implement and test the DCS interface Alice EMCAL Meeting, July 2nd 2007

  8. Summary • LVDS Link prototyping issue (test to be scheduled) • Agreement on link protocol (no counter proposal since Frascati)  High speed serializer provided to local trigger (TRU) by LPSC • Open questions: • ADC channel numbering versus physical location (to be confirmed or a new map ???) - Region orientation (mirroring between A and C side ???) Alice EMCAL Meeting, July 2nd 2007

  9. SPARES Alice EMCAL Meeting, July 2nd 2007

  10. TRU-STU Serial link specification Reference clock is issued by STU Returning serialized data phase unknown, calibration required at startup 1) Phase alignment: adjust the data input delay, when correctly tuned the words sequence that is read is always the same over several thousand samples. (IDELAY functionality) 2.5ns tsu th data data clk clk GOOD BAD 2) Character alignment: Once the input delay is properly tuned, the proper frame alignment has to be found out of 6 possibilities (BitSLIP module). MSB 100001 000011 000110 001100 011000 110000 LSB 001000 000100 000010 000001 100000 010000 GOOD GOOD Alice EMCAL Meeting, July 2nd 2007

  11. EMCAL layout (2/2) Confirmation of the ADC channel affectation vs geometrical position The ADC channel number has to be known by STU, in order to compute the triggers For instance, one 4X4 window is channel 5,6,9 and 10 Alice EMCAL Meeting, July 2nd 2007

  12. One SuperModule Electronics 1 FEE (Front End Electronics): - 32 analog inputs - 8 2X2 towers analog sum output to TRU - Readout by RCU 1 RCU (Readout Control Unit): - Readout 18 FEE (1/2 SM=1.5 TRU region) - Readout 1 (or 2) TRU 1 TRU (Trigger Region Unit): - receive Fast OR from 12 FEE (8*48 towers) - digitize 96 FastOR inputs at the machine clock frequency - compute local L0 trigger - provide 5 samples integrated data to STU upon global L0 reception crate 36 FEE 3 TRU 2 RCU GTL bus 32 towers /FEE Alice EMCAL Meeting, July 2nd 2007 1152 towers

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