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Synthesis of sequential circuits. Steps in synthesis of a sequential circuit Specify the FSM (state table or state diagram) Minimize the states State assignment/encoding Specification:. 0/1. 0/0. S 3. S 1. S 4. 1/1. 1/1. 0/0. 0/1. 0/1. 1/0. 1/1. S 2. S 5. 1/1.
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Synthesis of sequential circuits • Steps in synthesis of a sequential circuit • Specify the FSM (state table or state diagram) • Minimize the states • State assignment/encoding • Specification: 0/1 0/0 S3 S1 S4 1/1 1/1 0/0 0/1 0/1 1/0 1/1 S2 S5 1/1
State minimization(Completely specified FSM) • Completely specified no don’t cares • Progressively refine a set of equivalence classes, j • For the state machine on the previous slide • 0 = all states in one class = {{S1, S2, S3, S4, S5}} • 1: distinguished on the basis of output value • 1 = {{S1,S2},{S3,S4},{S5}} • 2: distinguished if NS for two states in a partition are in different partitions. • Example: For x=1, NS for S3 {S1,S2}; NS for S4{S5} • 2 = {{S1,S2},{S3}{S4},{S5}} • Continue finding j+1 given j in a similar way • Stop when j+1 = j since this implies that k = j for all k > j • In this example, 3 = 2 • Final set of equivalence classes = {{S1,S2},{S3}{S4},{S5}}
State minimization(Completely specified FSM) – Contd. • Final set of equivalence classes = {{S1,S2},{S3}{S4},{S5}} • State table shown at right • Complexity: • Let ns = # states • At most O(ns) iterations • Each iteration is O(ns) • Total complexity is O(ns2) • A more clever implementation can achieve O(ns log ns)
State minimization(Incompletely specified FSM) • Idea of equivalence does not hold any more • Equivalence involves • Reflexivity • (si <comp> si) • Symmetry • (si <comp> sj) (sj <comp> si) • Transitivity • (si <comp> sj) and (sj <comp> sk) (si <comp> sk) • For the state table here, looking at compatibility only in terms of the output value (similar to constructing 1 for a completely specified FSM) • s1 <comp> s2, s2 <comp> s3 but s1 is not compatible with s3 • Need to work with compatibilities instead of equivalences
State minimization(Incompletely specified FSM) – Contd. • Example: state table shown on previous slide • List (possibly) compatible states and clearly incompatible states • List conditions under which states could be compatible CompatibleIncompatible {S1,S2} {S1,S3} {S1,S5} {S3,S4} {S1,S4} {S2,S3} {S1,S5} {S2,S5} {S2,S4} {S3,S4} {S3,S5} {S3,S4} {S2,S4}, {S1,S5} {S4,S5} • {S1,S5} are compatible if {S3,S4} are compatible • Now use list of incompatible states to iteratively strike out states from compatible set and move them to the incompatible set • No such update possible here, although in general it may be possible • Combine now as {S2,S3,S4} {S1,S5} and {S1,S5} {S3,S4}: consistent • Result: combine {S2,S3,S4} into one state and {S1,S5} into another
State encoding • Assign Boolean codes to states • Two extremes • One-hot encoding: n bits for n states, only one bit set to 1 • Example: S1 = 1000, S2 = 0100, S3 = 0010, S4 = 0001 • Large # of state bits (and hence FF’s), simple combinational logic due to extensive don’t care space • Minimum-bit encoding: log2 n bits for n states • Example: S1 = 00, S2 = 01, S3 = 10, S4 = 11 • Small # of state bits, possibly more complex combinational logic • More commonly used • Can also be in between the extremes
01 00 01/1 01/1 11 State assignment heuristics • “Fanout oriented” • Same NS from two PS under a given input should be assigned neighboring codes • Example: two inputs X1,X2 and one output Z • Rationale: state table will include which implies that 0-01 fon(NS2), fon(NS1), fon(Z)
State assignment heuristics – contd. • “Fanin oriented” • If a PS goes to two different NS’s, they should be assigned neighboring codes • Example: two inputs X1,X2 and one output Z • Rationale: state table will include which implies that 011- fon(NS1), fon(Z) 01 10/1 11/1 11 10
A simple state-assignment algorithm • Considers fanin oriented case only and defines “attractions” • Construct matrices • ns x ns between states • Entry (i,j) = # of transitions from i to j • ns x noutputs between states and outputs • Entry (i,j) = # output transitions with value 1 0/0 S1 1/1 1/1 0/0 1/0 S3 S2 0/0
State assignment algorithm • Attraction metric between states Si and Sj = Nb PSi PSjT + zi zjT where Nb = # state bits, PSk = row k of state matrix zk = row k of output matrix • Attraction12 = 2[110][101]T + [1][0] = 2 • Attraction23 = 2[101][101]T + [0][1] = 4 • Attraction13 = 2[110][101]T + [1][1] = 3 • Build attraction graph • Start with node with max sum of edge attractions and assign it an encoding (here, S3 is arbitrarily assigned 00) • Assign encodings in order of attraction to neighbors to reduce Hamming distance (here, S2 = 01, S1 = 10) • Repeat until all states are assigned codes (here, we are done) 10 S1 2 3 4 S3 S2 00 01