1 / 7

Learning by doing

Learning by doing. Course : Digital system design using Verilog. Project based learning. The whole course is based on a project i.e., processor design . The course have been divided into 5 UNITs (17 modules).

maya
Download Presentation

Learning by doing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Learning by doing Course : Digital system design using Verilog

  2. Project based learning • The whole course is based on a project i.e., processor design. • The course have been divided into 5 UNITs (17 modules). • Tasks are to designing small blocks of the processor. In the end it is adding up all the block and design the final processor. • From this course student will not only learn Verilog but also how to complete a big project by dividing intro smaller blocks.

  3. Concepts • Each module covers 3-4 Just in time ppts for basic understanding of the module. • Few external links or resources (pdfs, ppts) are also added in each module. • Animation work is still in process.

  4. Interative • We have added one module 1.2 in which we will tell them to download the software and install it. • Simulate the circuits. Check the waveform • Generally in TASKS at least one task is there in which student have to do something like Simulation. • Embedding the simulator into web is still in process.

  5. Analysis • Each module cover sufficient number of example. • Students have been taught Verilog Step-by-Step. • [under process] Few research papers related to verilog and digital system design have yet to be added. So that students will know the background of Verilog.

  6. Innovative • [optional] questions have been given across the course in each module for those who are interested in advanced topics. • [Research Project] apart from regular project which is designing a processor few research projects have been added in the module 0.

  7. JNTU syllabus • The modules are prepared a/c to JNTU syllabus for verilog course.

More Related