A low-power efficient direct digital frequency synthesizer based on new two-level lookup table

1. A low-power efficient direct digital frequency synthesizer based on new two-level lookup table Presenter： Cheng-Hsun Liang Number:9766200311 Kun-Tse Lee, Jin-Jia Chen Department of Electrical Engineering, NCUE Changhua, Taiwan 500, ROC

2. Outline • INTRODUCTION • New TWO-LEVEL LOOKUP TABLE ALGORITHM • The ARCHITECTURE OF THE PROPOSE DDFS • SIMULATION • CONCLUSIONS

3. INTRODUCTION • This work presents a low power direct digital frequency synthesizer (DDFS) by using a new two-level lookup table algorithm. • The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. • DDFS is an important device for wireless communication systems. • Most DDFS architecture can be divided into two types ROM-based DDFS and ROM-less DDFS.

4. Conventional architecture of the ROM-based DDFS Fctri deciding the accumulating step Fclk being the operation frequency The output frequency Assume phase accumulator is M-bit.

5. ROM-less DDFS • The other architecture of DDFS replaces the lookup table ROM with non-linear DAC. • This type of DDFS is usually called ROM-less DDFS. • The ROM-less DDFS consumes less power and chip area than the ROM-based DDFS. • This paper provides a new algorithm to reduce further the size of lookup table ROM for low-power purpose.

6. New TWO-LEVEL LOOKUP TABLE ALGORITHEM The algorithm uses trigonometric double angle formula to divide cosθ, sinθ into two parts as: The maximal error function can write as: The MSB address of the phase θi , while the (θ - θi) represents the LSB address of the phase θ. The equation also can be rewritten as: The maximal sine and cosine error function can be estimated by Taylor-series as:

7. In table 1, we can find that θk = (a tan 2^-k)/2π and tan 2^-k≒2^-k when k≧7. By the reason, we only require to store tanθ data in lookup table ROM, tanβ≒β.

8. The ARCHITECTURE OF THE PROPOSE DDFS Table 2 Performance summary of the new DDFS The architecture of the proposed DDFS

9. SIMULATION figure 4 Real cosine output waveform v.s. ideal cosine waveform figure 3 Simulation SFDR of the proposed DDFS

10. SIMULATION We synthesize the new architecture of DDFS by TSMC 0.35μm cell-based standard cell. The simulation result is shown in the table.

11. CONCLUSIONS • The proposed DDFS has the advantages of low-power, small chip area and low computational complexity • In addition to, it uses cell-based standard cell to reduce design time. • It can be changed different technology process in short time. • The power efficiency of our work is 0.81 mW/MHz and 38% less than that of conventional DDFS. • The algorithm can efficiently save ALU cells andpower consumption in DDFS.

12. The End Thank you for your attentions !