Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture

1. Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture Usman Hai B.Engg Electronics Dept NED UEET Muhammad Nadir Khan B.Engg. Electronics Dept. NED UET Muhammad Saad Imran B.Engg Electronics Dept NED UET Muhammad Rehan B.Engg Electronics Dept. NED UET 0-7803-9262-0/05/@2005 IEEE Rostrum： De-Ji Liu Date：12/11/2007

2. OUTLINE • ABSTRACT • INTRODUCTION • ALGORITHM • PROPOSED DESIGN • SIMULATION RESULTS • CONCLUSION • REFRENCE

3. ABSTRACT • A low-power, high speed direct digital frequency synthesizer (DDFS) is presented. • Some approximations are used to avoid using a large ROM look-up table to store the sine values in a conventional DDFS. • Significant saving in power consumption, to the compressed ROM. • To demonstrate the proposed technique, a DDFS has been implemented using Taylor's series.

4. INTRODUCTION The basic architecture of a DDFS for sine function generation is shown in Fig 1.

5. The minimum frequency resolution of the DDFS is following： The output frequency, fo, is controlled by the value of the N-bit input word (Frequency Input Word FIW)

6. ALGORITHM Sine function can be implemented based on the following Taylor series approximations： We simplify the calculation by storing only the amplitude of sampling point of Sin（ θo）, its corresponding slope is just the amplitude of another Sampling point of Sin（π/2-θo）. We can implement the Taylor series approximation with Eq.（2）only storing sample’s amplitude. The ROM size can the be reduced greatly without any accuracy degration.

7. PROPOSED DESIGN

8. The m+n+3 "MSBs" of N bits at the output of the accumulator are used for subsequent blocks as the phase, θ. The most significant 3-bits of the phase accumulator output are used to control the generation of the full sine wave . m bits (MSBs of m+n remaining bits of the phase are used to address the ROM for sine and cosine. The lower significant n bits (LSBs of m+n bits of the phase) represents (θ -θo).

9. 39db 45db Simulation results with different LUT sizes SIMULATION RESULTS

10. CONCLUSION • A low-power, high speed direct digital frequency synthesizer architecture has been presented. • It uses compressed ROM technique which employs half period of a clock for sine function resulting in a small ROM look-up table, to saving in power consumption.

11. REFRENCES • [1] D.A. Sunderland, "CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications", IEEE J. Solid-State Circuits, VOL.19, pp 497-505, Aug 1984. • [2] H.T. Nicholas, "A 1 50-MHz Direct Digital Frequency Synthesizer in 1.25-um CMOS with. 9OdBc Spurious Perfonnances", IEEE J. Solid-State Circuits, VOL.26, pp 1959-1969, Dec 1991. • [3] A. Madisetti, "A 100-MHz, 16-b, Direct Digital Frequency Synthesizer with 100-dBc Spurious-Free Dynamic Range," IEEE J.Solid-State Circuits, VOL.34, pp 1034-1043, Aug 1999. • [4] Mortezapour, S.; Lee, E.K.F." Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter" Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 10 , Oct. 1999, pp: 1350 -1359. • [5] H.T. Nicholas, H. Samueli, and B. Kim, "The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects", in Proc. 42nd Annu. Freq. Contr.Symp., 1988,pp.357-363.

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