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Razor: A Low Power Processor Design

Explore the implementation of Razor technology in processor design for energy efficiency, addressing the need for higher clock speeds and low power consumption through dynamic voltage scaling and error correction.

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Razor: A Low Power Processor Design

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  1. Razor: A Low Power Processor Design Presented By: - Murali Dharan

  2. Power Aware Computing • Primary concern in design of processors and SoCs • Paradox of need of higher clock frequencies and low power designs f α Vdd E = SCV2dd + VddIleakT T. Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 57

  3. Solution • Dynamic Voltage Scaling (DVS) • Periods of low processor utilization exploited by lowering clock frequency • Critical supply voltage • Min. supply voltage resulting in correct operation • Should be sufficient to factor in global and local variations D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003, pp.7

  4. Voltage Margins • Process Margin • Result from manufacturing variations • Ambient Margin • Slower circuit operations at higher temperatures • Noise Margin • Safeguard against different noise sources T. Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 58

  5. Basic Idea Proposed • Tune the supply voltage by monitoring the error rate during operation • Accounts for both global and local variations • Eliminates need for “Voltage Margins” • Sub critical voltage cause trade off between error recovery and power savings • Savings up to 64.2% with penalty of <3% D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003, pp.7-8

  6. Implementation of Error Correction Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 60

  7. Experimental Results Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 59

  8. Prototype Implementation Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 62-63

  9. Energy Optimal Characteristics Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 63

  10. Future Research Areas • Implementation of Razor Technology in the design of Control Logics • Implementation of Razor Technology in the design of Memories Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp. 63

  11. References • “Making Typical Silicon Matter with Razor” • Todd Austin, David Blaauw, Trevor Mudge University of Michigan; Krisztián Flautner ARM Ltd. • “Razor: A Low Power Pipeline Based on Circuit-Level timing Speculation” • Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge Advanced Computer Architecture Lab University of Michigan and Krisztián Flautner ARM Ltd. • IEEE Spectrum Feb. 2008 Edition “Intel and ARM are Exploring Self-Correction Schemes to Boost Processor Performance and Cut Power” by Neil Savage

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