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CSC’s & Post LS3 TriDAS

CSC’s & Post LS3 TriDAS. Oliver Buchmueller Imperial College Wesley H. Smith U . Wisconsin TPSWG Meeting with CSC Team November 19, 2012 Outline: Introduction to architecture issues Summary of constraints from other subsystems Questions for CSC Subsystem.

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CSC’s & Post LS3 TriDAS

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  1. CSC’s & Post LS3 TriDAS • Oliver Buchmueller • Imperial College • Wesley H. Smith • U. Wisconsin TPSWG Meeting with CSC Team November 19, 2012 Outline: Introduction to architecture issues Summary of constraints from other subsystems Questions for CSC Subsystem

  2. Need Longer Latency/Higher Rate • L1 Trigger Latency Increase: • Combination with tracking logic • Increased algorithm complexity • Long enough for secondary vertices? • Asynchronous links or FPGA-integrated deserialization require more latency • Finer result granularity requires more processing time • L1 Trigger Rate Increase • Tracking trigger does not address hadronic triggers, e.g. • Higgs program: H(125)bb, H→ττ, • Hadronic triggers for other searches

  3. Architecture • Option of L1 Trigger latency of 20 μsec, rate of 1 MHz & HLT output rate of 10 kHz is feasible for all subsystems(pending rebuild of EB electronics & questions of CSC efficiency), DAQ & Computing, but has significant cost (funds, personnel, time) & is under serious consideration. • information from subdetectors, DAQ & computing accumulated. • Input from Technical Coordination on planning for replacement of EB electronics during LS3 (next slide). • Propose to ask all development for Phase 2 be compatible with L1 Trigger latency of 20 μsec, rate of 1 MHz & HLT output rate of 10 kHz. • Propose to ask all subdetectors to present a plan to operate with L1 Trigger latency of 20 μsec, rate of 1 MHz & HLT output rate of 10 kHz • Cost & schedule of any modifications/updates • Performance (e.g. trigger & reconstruction efficiency) of subdetector system, including any modifications/updates, with with L1 Trigger latency of 20 μsec, rate of 1 MHz & HLT output rate of 10 kHz • Final decision to be taken next year.

  4. Replace EB Electronics in LS3 • Conclusions from Technical Coordination Working Group charged by Upgrade PMs: • “Assuming a dedicated workshop with six parallel working lines...26 months of working time will be needed for the entire project.” • “As for most of the time the detector has to be fully opened with the barrel wheels on the vacuum tank of the solenoid, parallel work on the muon systems, the HCAL and the ECAL endcap will be severely restricted.” • Implication: • Most updates of on-detector CSC electronics would need to be complete by end of LS2.

  5. Questions for CSC Community(Thanks for your input!) • What is known about performance of CSC readout with 20 usec latency & 1 MHz L1A w/o further replacement of CFEBs w/DCFEBs? • Are there reductions in L1A rate & latency that would make appreciable difference w/o further replacement of CFEBs w/DCFEBs? • What possibilities are there for partial replacement of CFEBs with DCFEBs in regions with higher occupancy & would these options also provide sufficient performance? • What is failure rate of CFEBs & what would we expect by 2018? • What would be required to plan partial or full replacement of all CFEBs w/DCFEBs during _LS2_? • What cost, resources and time would it take? • What modifications would be required to DCFEBs to reduce power & what cost would these modified versions have given less performant& lower cost/power FPGAs & would these be satisfactory? • What other boards would need replacement along with the CFEBs? • And finally, how should we proceed?

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