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GBT Project Status

GBT Project Status. Paulo Moreira On behalf of the GBT team CERN, 9 th September 2013. GBLD Status. GBLD V4.1 Fully functional Excellent performance Total dose radiation hardness proved SEU robustness tests to be done in October 2013 Device is production ready DM metal stack

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GBT Project Status

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  1. GBT Project Status Paulo Moreira On behalf of the GBT team CERN, 9th September 2013 Paulo.Moreira@cern.ch

  2. GBLD Status • GBLD V4.1 • Fully functional • Excellent performance • Total dose radiation hardness proved • SEU robustness tests to be done in October 2013 • Device is production ready • DM metal stack • Dedicated/Shared production 4.8 Gb/s, pre-emphasis on Total jitter: ≈ 25 ps Paulo.Moreira@cern.ch

  3. LpGBLD Status • Low power GBLD • VCSEL driver only: • Lower modulation current: • 12 mA max • Power consumption reduced by 40% • VCSEL choice is determinant • Min: 138 mW • Max: 325 mW • Uses the LM stack: • It can be fabricated with GBTIA and GBTX • Performance is good at ambient temperature: • At high temperatures (> 70) there might an issue! • To be investigated further Paulo.Moreira@cern.ch

  4. GBTIA Status • GBTIA V2.0 / V2.1 • Fully functional • Excellent performance • Radiation hardness proved • Tested up to 200 Mrad (SiO2) • Device is production ready • LM metal stack Paulo.Moreira@cern.ch

  5. GBTX Status • The GBTX is available for testing since May 2013 • A via was shorting a power and a ground plane in the package making the ASIC unusable! • Using a CNC machine and the package layout information it was possible to drill the via and recover the ASIC for testing: • A few e-Links were lost but most of the functionality could be tested • New packages were produced by ASE this time without the short! • ASICs now being tested • Almost 100% of the chip functions have now been tested: • A couple of digital functions to be tested still • The CDR and the phase-shifter problems are now solved! • The new functionality works fine • The chip is “100%” functional and could be distributed to the users for prototyping Paulo.Moreira@cern.ch

  6. GBTX Status Not everything are roses! • TX eye-diagram is not as good as for the SerDes! • Possibly due to the “reshuffling” of the phases to improve the low frequency ability (done to correct the “evil bit” problem)! • But not yet sure! • Maximum: 5.4 Gb/s • 6.0 Gb/s for SerDes • Lock mode with the REF-PLL “not” working: • Now understood why! (It was working on the SerDes) • Not a critical bug the DAC locking mode works very well • CDR “Frequency Detector” is not doing its function very well! • Due to the low gain of the FD when the frequency difference is relatively small charge-pump unbalance introduces a frequency error • The circuit works but require a rather high precision in the reference frequency • Actually compensates well for low frequencies but not high • XPLL start-up needs to be improved. • Crystal motional resistance higher than the design value (“incomplete” information from the manufacturer) • Possible problem with the watchdog, but still to be confirmed! • Maybe related with the Frequency detector problem mentioned above Paulo.Moreira@cern.ch

  7. eCDR • The e-CDR prototype was submitted to validate: • The ePort CDR macro-cell • The referenceless data-locking mechanism • (Chip contains also an ePLL) • Chips have just been received from the foundry • The test setup is ready • Testing will start soon • Filip will present the work at TWEPP Paulo.Moreira@cern.ch

  8. GBTX What’s Next • Two SEU test runs: • October / November • New GBTX prototype February 2014 • ASIC: 80k • Packaging: 6k • Production of the SAT board as a development KIT (cost to be partially recovered from the users): 70k • New ICT board (connectors and mechanical rigidity are giving problems): 20k • GBLD10 prototype February 2014 • ASIC: 16k • Packaging: 5k • Testing: 10k Paulo.Moreira@cern.ch

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