Contact

1. Contact Reinier A. van Mourik, MSc PhD Researcher Spintronics Devices IBM / Eindhoven University of Technology IBM Almaden Research Center650 Harry Rd San Jose, CA 95120 USA Tel +1 408 927 2501 Fax +1 408 927 2510 Mobile +1 408 821 4559 rvmourik@us.ibm.com

2. Reinier van Mourik1,2, Li Gao1, Brian Hughes1, Charles Rettner1, Bert Koopmans2, Stuart Parkin1 1. IBM Almaden Research Center, San Jose, CA2. Eindhoven University of Technology, Eindhoven, the Netherlands Reliability of Signal Propagation in Magnetostatically Coupled Arrays of Magnetic Nanoelements

3. Nanomagnetic logic - principle 1. Introduction Majority gate A M output read B D A • Energy-efficient • Non-volatile • Fast • Radiation resistant B D M C C Majority gate is programmable NAND/NOR gate  Full logic set

4. Outline 1. Introduction • Experiment and simulation: inherent unreliability • Alternative for conventional NML: Domain wall clocking

5. ~70Oe d514 Experiment setup 2. Error rate in NML devices measurement • fabrication The RH curve of the MTJ shows output of device Artificial input biases first dot according to reset direction MFM shows state of each dot

6. Single device: shot-to-shot results 2. Error rate in NML devices input output Output MTJ state alternates accordingly when alternating input direction.

7. Many devices: device-to-device results clocking cycle, input +x 2. Error rate in NML devices • 68/158 (43%) of devices contain errors • 116/123 (94%) of devices evolve to exact same state • 66/79 (84%) of devices evolve to exact inverse state repeat clocking cycle, input +x clocking cycle, input -x Success/error is highly reproducible, thus inherent in device.

8. Error rate in signal propagation - simulations 2. Error rate in NML devices Last NM evolves before signal reaches it • Device-to-device error rate tends to 50% as length increases Errors are caused by last magnet evolving early.

9. Domain wall clocking - principle 3. Domain wall clocking Fringing field from domain wall in perpendicularly magnetized material can reset nanomagnets.

10. DW clocking – experimental setup 3. Domain wall clocking Domain wall injection line Hall bar hall bar read • 1. inject DW DW nanodotsPy 60x90x20nm PMA nanowire 60-180nm wide 2. propagate DW by H field • 3. read resistance change in AMR and Hall bar AMR read

11. DW clocking - results Prepare device in incorrect state End in correct state Pass DW underneath 3. Domain wall clocking DW clocking demonstrated in 1- and 2-magnet devices

12. Conclusion • Nanomagnetic Logic is magnetic alternative to CMOS logic • Analysis done of reliability of NML devices with integrated output • Errors are reproducible per device and tend to 50% among devices. • Domain Wall clocking is demonstrated as alternative clocking scheme slides & contact: http://tinyurl.com/RvM-IBM