Metrology Roadmap 2002 Update

1. Metrology Roadmap2002 Update Europe Uli Mantz (Infineon) Alec Reader (Philips Analytical) Mauro Vascone (ST) Japan Mashino Ikeno (Mitsubishi) Toshihiko Osada (Fugijitsu) Korea DH Cho (Samsung) Taiwan Henry Ma (EPISIL) US Steve Knight (NIST) Alain Diebold (Int. SEMATECH)

2. AGENDA • 2002 ITRS Changes • Overview 2001 • 2001 Difficult Challenges • Lithography Metrology • FEP Metrology • Interconnect Metrology • Materials & Contamination Characterization • Grand Metrology Challenges

3. 2001 Metrology Requirements Summary

4. 2002 ITRS Changes Printed Gate CD now Driver Near term RED becomes orange with manufacturing controlling to range larger than ITRS LER becomes off-line measurement Methods now being tested RED goes to Yellow

5. Litho Process part of total CD budget • Litho Process range - Litho 2/3 Etch 1/3 • Use Process Range for Physical (Etched) Gate for both Printed and Etched Gate • Variances add as sum of squares • Etched Gate • 90 nm node Process range for 37 nm physical i.e., etched gate, of 3.7 nm 3 (i.e. plus or minus 10%) • 2/3 of (3.7 nm)2 = 9.12 nm which gives 3 nm 3 for Litho Process Range • 3 Precision for P/T of 20% is 0.2 x 3 nm = 0.6 nm • Make Precision of Printed gate match that of Etched Gate and Result is that Printed Gate now requires better precision

6. MODE ENERGY Conventional Imaging Low Energy High Energy Holography The High Energy CD-SEM (2) The Point Projection Microscope (3) The CD-SEM (1) The CD-TEM (4) CD-SEM Possibilities

7. Interconnect Clarification for Void Detection in Copper Lines • Detection of post deposition and anneal process voids at or exceeding listed size (nm) when these voids constitute 1 % or more of total metal level conductor volume of copper line and 5% of vias. [B]

8. SCOPE • Overview • Microscopy • Control of Statistical Processes • Lithography Metrology • Front End Processes Metrology • Interconnect Metrology • Integrated Metrology • Materials and Contamination Characterization • Packaging Metrology • Reference Materials and Standards

9. New to – Five Difficult Challenges ³ 65nm / Before 2007 • Key requirement for Cu/Damascene metrology is void detection in Cu lines and pore size distribution (find killer voids and pores) • Scribe line shrinkage reduce test structure area making high precision measurements difficult in scribe lines.

10. New to – Five Difficult Challenges  65nm / After 2007 • Determination of manufacturing Metrology when device and interconnect technology remain undefined.

11. GAPS in FAB Ready Metrology • 3D CD for Mask and Wafer for lines and contact/via and long term capability for CD • Optical and Electrical Metrology that controls high k plus interface • Void detection in copper Lines • Killer Pores in low k • Sidewall barrier layer control below seed Cu

12. Difficult Challenges before 65 nm / 2007 • Factory level and company-wide metrology integration • Impurity detection (especially particles) at levels of interest for starting materials & reduced edge exclusion for metrology tools. • Control of high-aspect ratio technologies such as Damascene challenges all metrology methods. Key requirements are void detection in copper lines and pore size distribution in patterned low k. • Measurement of complex material stacks and interfacial properties including physical and electrical properties. • Measurement test structures and reference materials.

13. Difficult Challengesafter 65 nm / 2007 Nondestructive, production worthy wafer and mask level microscopy for critical dimension measurement for 3-D structures, overlay, defect detection, and analysis. Standard electrical test methods for reliability of new materials, such as ultra-thin gate and capacitor dielectric materials, are not available. Statistical limits of sub-65 nm process control. 3D dopant profiling. Determination of manufacturing Metrology when device and interconnect technology remain undefined.

14. GAPS in Litho Metrology • Precision of CD-SEM • Proof of 3D CD for Tilt Beam CD-SEM • Commercialization of 3D software for top-down CD-SEM • Depth of Field Issues for CD-SEM • Reference Materials for 65 nm node and below • Standard method for Precision of Discrete CD Library • Probe Tip Technology for CD-AFM

15. Changes to Lithography Metrology • Accelerated MPU Gate Length dilutes advances in CD Measurement • Will 15% Process 3 be adopted?? • Addition of Line Edge Roughness Metrics • Overlay may face difficulties associated with mixing exposure tools • e.g., 2 different 157 nm exposure tools for via & metal trench (or 157 nm for lines & Electron Projection for Via)

16. Line Edge Roughness Requirements AVE CD = 150 nm Line Edge Roughness Correlated to Leakage Current Increase Patterson, et. al., SPIE 2001 Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi

17. Why are CD Measurement Requirements RED? • There is no universal metrology solution for all CD measurements. • e.g., Scatterometry meets Focus-Exposure precision needs to (70 nm node?) for resist lines but not for contacts (yet). • Can Scatterometry measure LER ? • 3D info needed for undercut gate, contact, and other structures. • Precision includes tool matching and near + long term measurement variation.

18. Gaps in FEP Metrology • Physical Metrology for high k gate stack • Optical Models for next High k (beyond ZrO2 and HfO2) • Commercial availability of high k optical model in software • Interfacial control for interface between high k and silicon • Electrical Metrology for high k gate stack • Application of Non-contact C-V to next High k (beyond ZrO2 and HfO2) • Comparison of non-contact electrical to C-V • USJ Metrology • Ultra Shallow Junction Metrology (USJ) • Dose/Junction Control • 2D Dopant Profiling with spatial resolution • Metrology for post CMOS • SOI ; SiGe ; Vertical Transistors

19. FEP Metrology • Optical and Electrical measurement of High  can be done for development but needs to be robust for manufacturing • Metrology for interface below High  needs R&D • USJ Metrology needs development for < 65 nm • FERAM needs fatigue testing for 1016 read/write cycles

20. Gaps in Interconnect Metrology • VOID Detection in Copper lines • Killer Pore Detection in Low k • Barrier / Seed Cu on sidewalls • Control of each new Low k

21. Interconnect Metrology • Random isolated void detection (size of 25% of line width) at < 1% in copper lines may not be measurable in-line • Max Low  Pore size of 5% of line width • Metrology for electrochemical deposition will be included in Metrology Roadmap

22. Materials Characterization Enables Process and Metrology Development Short term: New Aberration Corrected Lens for STEM/TEM Long Term: Atom Probe Dave Muller - Lucent

23. 2001 Grand Challenges • Development of Metrology tools in time. • Rapid non-destructive metrology forCD, overlay, defect detection and line edge roughness that meets ITRS timing and technology requirements.

24. Will Market Risks allow for innovation?

25. US TWG Writing Team Peter Borden (Boxer-Cross) FEP Murray Bullis (SEMI) Intro Alain Diebold (Int. SEMATECH) Intro/Edit Jack Martinez (NIST) Standards Cecilia Martner (Applied Materials) Interconnect Clive Hayzelden FEP Dick Hockett (CEA/PHI Metrics) Materials Char. Steve Knight (NIST) Statistical Limits Noel Poduje (ADE) FEP Michael Postek (NIST) Microscopy Brad van Eck (Int. SEMATECH) Int. Meterology Andras Vladar Microscopy

26. Backup

27. New Metrology Need: Standardized Statistics for Discretized Data • Some new methods fit measurement to a discrete set of possible results • This could result in artificially good precision values that do not really evaluate process control capability

28. 2001 Metrology Requirements Summary

29. Novel Methods for FEM control Optical CD using Overlay System Dualbeam FIB FEI e.g. 150 nm lines 300 nm pitch Dose  Automatic cross-sectioning, imaging and metrology from all sites of the FEM Focus  L S

30. Leakage Current correlated to Line Edge Roughness Center of data at 150 nm channel length with drive current of 500 mA/mm Leakage plotted versus active width of transistor The two lines show the dependence for the case of low and high line edge roughness. Units for leakage current are A/mm, plotted on a logrithimic scale Patterson, et. al., SPIE 2001 Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi

31. CD-SEM a Potential Solution for Wafer and Mask / R&D + Production • Barriers and Solutions • 193 & 157 nm Resist Damage • lower dose images • Lineshape • tilt beam SEM vs software • Precision Improvements • new nano-tip source • Depth of Focus • new SEM concept needed • Ultimate Limit of CD-SEM • ~ 5 nm for etched poly Si Gate Sato and Mizuno, EIPBN 2000, Palm Springs, CA

32. Acoustic ISTS Picosecond acoustics X-ray reflectivity X-ray fluorescence Non-contact resistivity 5 Potential Solutions all expected to meet precision requirements some are extendable to patterned wafers Interconnect Metrology SolutionsBarrier/Seed Cu Films

33. Voids in CopperPore Size/Killer Pores in Low k • Random isolated void detection in copper lines may be used in development at levels above the < 1% metric • <1% may not be measurable

34. Metrology & New Structures Source Vertical Transistor Gate Gate Drain What are the new Structures???