Metrology Roadmap ERD and ERM Update - Stresa

1. Metrology RoadmapERD and ERM Update - Stresa Europe Ulrich Mantz (Infineon) Dick Verkleij (Philips) Mauro Vasconi (ST) Japan Yuichiro Yamazaki (Toshiba) Kazuo Nishihagi (Technos) Korea Taiwan US Dan Herr (SRC) Steve Knight (NIST) Alain Diebold (Int. SEMATECH)

2. New Business • Established link with Emerging Research Materials group of ERD • ERM to report requirements • Metrology Reports Methods and Discussion • Provided update on aberration corrected TEM and 3D TEM developments • Awaiting changes in Process Tolerance for Gate CD

3. New Cross-TWG Business • Litho TWG • Discussed AEC/APC needs for track • CD shape monitoring vs CD for tool monitoring • LWR LER - off line or in-line? • FEP • Need to participate in Film subgroup for mobility and stress measurement discussions • Doping in FINs; FIN CD height and width; FIN shape; defects and film thickness on sidewalls • Metal Gate work function measurement needed • Factory Integration • AEC/APC needs discussion –Data accessibility and integrity issues • Interconnect – later today

4. AGENDA • 2003 ITRS Changes and 2004 Activities • Lithography Metrology • FEP Metrology • Interconnect Metrology • Key Challenges

5. 45 - 32 nm Node Metrology R&D Materials available 10 nm structures difficult to obtain ITRS Challenge Tool Set Exists 65 nm Node Leading Edge Tool Specifications set R&D 45 nm Node Early R&D 32 nm Node

6. Metrology Critical Challenges Five Difficult Challenges ³ 45 nm, Through 2009 • Metrology Integration • Starting Materials and In-line Metrology for strained Si, SiGe, and SOI • Control of high-aspect ratio technologies including copper void detection • Measurement of complex material stacks and interfacial properties • Measurement test structures and reference materials

7. Metrology Critical Challenges Five Difficult Challenges < 45 nm, Beyond 2009 • Nondestructive, production worthy, wafer and mask level microscopy for CD and overlay • New strategy for in-die metrology must reflect across chip and across wafer variation • Statistical limits of sub-45 nm process control • Structural and elemental analysis at device dimensions. i.e. materials characterization • Development of manufacturing metrology when device and interconnect technology remain undefined

8. 2003 ITRS Changes

9. 2004 ITRS Survey on Litho Control • 2003 Litho Process range Feature Process Range 3Litho/Etch Division • Isolated Gate10%Litho 4/5 Etch 1/5 • Dense Lines 15% Litho 2/3 Etch 1/3 • Contacts 10% Litho 2/3 Etch 1/3 • FEP, PIDS, Litho, and Metrology expressed concerns about real CD Process range values vs Roadmap • ITRS will survey several TWGs

10. 2004 ITRS Activities • Update all Technology Requirements Tables • Initiate new work for 2005 Rewrite • Look at Litho CD Potential Solutions • Expand Overlay Section • Expand discussion of new areas such as SEM overlay • Look at new areas of FEP activity • Local Stress Measurements • Metal Gates • Look at Interconnect long term needs

11. Metrology Questions for LithoApril 2004 - Stresa 05 05 05 • For AEC/APC In addition to Resist Trim CD what other measurements are a priority. • “ CD in resist ; need to measure in device area for pattern shape for features known to be effected by OPC – integrated micro-inspection ; overlay – also may need specific feature level inspection” • In track AEC/APC is 3D CD needed. Is it a tool monitor or a real CD metrology. • “see above” • LWR-LER what kind of control - is it set for a process or is routine monitoring needed. • “ Routine monitor maybe – FEP/PIDS/Litho/Metrology issue; number reported for LER depends on how it is measured; Metrology tables would reflect how to do the measurement – Litho tables reflect what requirements for process are;

12. Metrology Questions for LithoApril 2004 - Stresa 05 04 • Profile info – Bottom vs Top CD see next page • Add Sidewall angle requirement/profile back into requirements table? Ask AMAG-OMAG • “ Etch process defines final profile” • “ ability to analyze slope of resist – lab centric measurement”

13. From FEP Table 71 a comments

14. 16 nm Node - 2018 6.35mm 152mm 152mm 40 nm mask line width 20 nm scattering bars 10 nm printed line width EUV 7 nm physical line width Litho Metrology Importance of Mask CD Tables CD Control Starts at the Mask Overlay and CD Control after Exposure CD Control after Etch

15. Red moved out in Litho Metrology Technology Requirements

16. 2004 Potential Solution Assessments • Conflicting Reports on high keV CD-SEM Damage • Impact of Metal Gate on CD-SEM and Scatterometry • Impact of Gate thickness on CD Measurement

17. FEP : High  Metrology • Metal Gate and high k both require metrology development • SOI and Strained Silicon • New Transistor Designs

18. Increasing Emphasis on Areas beyond High k • Increase in Mobility by using local stressing of transistors – Call for stress metrology by FEP • Metal Gates increasingly important • New transistor designs are already past R and into D. Example: FIN-FETs require metrology • Strained SOI, GeOI considered longer term substrates • Crystal Defect mapping including on patterned wafers metrology requirement for new substrates • Mobility measurements are key

19. 90 nm node High Volume CMOSStrained Si substrates not used PMOS Compressive Strain increased hole mobility 45 nm NMOS Tensile Stress SiN Layer increased electron mobility From T. Ghani, et. al., IEDM 2003, p 978. Courtesy Intel

21. Metal Gate impacts selection of Metrology q Models can include interface layer d Phase shift = q 2 d sin l • If Metal Gate is used then either • Integrate metrology with process tool • try X-ray Reflectivity Thanks to Rich Matyi 4 nm HfO2

22. Metrology questions for FEP April 2004 Stresa 05 05 05 • What is really needed for Mobility for advanced structures? • “Mobility requirements are in PIDS tables – one can extract mobility from I-V + C-V measurements – Thermal Films subTWG is planning to develop requirements for strained Si for 2005 –” • Local stress at transistor level is difficult to measure physically – What do you really need? • “The more local the better … qualitative is better than no measurement” • Metal Gates increasingly important – Other than gate thickness and roughness what other measurements are needed. • “Work function - Resistivity”

23. Metrology questions for FEP April 2004 Stresa 05 05 • Are there changes in starting materials requirements such as in Site flatness and contamination? • “Site flatness remains as a requirement Contamination and other requirements are surveyed regularly, and changes are expected for 2004 and 2005. High k contamination requirements will be added to Surface Prep” • What are priorities for FINFET and advanced non-classical CMOS metrology requirements? • “Doping in FINs; FIN CD height and width; FIN shape; defects and film thickness on sidewalls”

24. Metrology questions for FEP April 2004 Stresa 04 05 • Are composition and concentration distribution with depth manufacturing or development measurements? • “Certainly for R+D, but uncertain for in-line The data is not yet available” • Is improving long term matching & stability of optical metrology tools a requirement for gate dielectric? • “Issue seems to true for many” • “C-V measurements for leaky films continues to be a problem”

25. Gaps in Interconnect Metrology • VOID Detection in Copper vias & lines now based on 1/10 via diameter • Barrier/Seed quality on sidewalls • Killer Pore Detection in Low kpore size distribution • Non destructive metrology for adhesion and  (at operating freq.) for patterned wafers

26. 2004 Interconnect Activities • Porous low k is being overshadowed by the need to lower k value of barrier layer and etch stops for 45 nm node. • Long term solution for interconnect is ambiguous.

27. Questions for Interconnect from Metrology – April 2004 Stresa 05 05 05 • What is beyond Cu/low k? • “Copper will remain M1 thru intermediate wiring, intra-chip global connections will become RF or Optical. Cooled conductors and superconductors are more speculative options. Nanotubes are more speculative” • Are there metrology issues associated with integrating wireless (e.g., high Q inductors resonators, etc.) and MEMS? • “Large features at upper levels with no big metrology issues. Stress is an issue for this and for conventional interconnect.” • Optical Interconnect between chips – any metrology issues -See Intel’s recent work • “Large feature at upper level with no big metrology issue.”

28. Questions for Interconnect from Metrology – April 2004 Stresa 05 05 05 • Is texture of metal films needed in your opinion? • “Alpha or beta Ta is probably a lab measurement during development. Sensitivity might drive its’s use in-line. Texture post copper anneal is not likely in-line. Grain size of copper is bigger issue. Electromigration is along interfaces with other materials. Capping Cu with e.g., selective W or CoWP reduces electromigration.” • What is your view about all the new potential in-line methods? X-ray pore size distribution. ? • “Process will be under enough control that this will probably be used during process development.” • Overlay issues for BEOL? Does box in box represent correct overlay errors? • “Not discussed much in Interconnect”

29. Questions for Interconnect from Metrology – April 2004 Stresa • Etch Stops need to be removed to lower effective k. Blind etch for trench etch stop. Micro-loading gives variability across chip. A good in-line etch measurement with multi-spot view of substrate for etch stop is needed. Roughness after etch needs to be controlled and varies with individual tool condition. • Through the wafer vias to connect chips will have metrology needs. • New processes have critical flow control – e.g., calibrating mass flow controllers – What is the tolerance? Standards? Point of use blending. Where is it on the roadmap? ISSUE for IRC 04??

30. ERD and ERMPremise: Aberration corrected TEM/STEM needed for nano-electronics • Latest TEM and STEM results show improved imaging for sub 0.1 nm beams. • We have not reached the limit where improving beam diameter does not improve imaging • Nanowires and nanotubes serve as ideal systems to test theoretical and experimental understanding of beam propagation and image formation. - reduced stresses and amorphous films on the surface

31. Concept Proven : Aberration Correction STEM – Batson, Dellby, and Krivanek, Nature 418, 617 (2002) Si(110) HR-TEM – Jai, Lentzen, and Urban, Microsc. Microanal. 10, 174, 2004. SrTiO3 Before After

32. Concept Proven : Aberration Correction HR-TEM and Focal Series Reconstruction – A. Ziegler, C. Kisielowski, R. Ritchie, Acta Mat. 50, 2002, 565 Si dumbell structure observed Si lattice Before After

33. Obj aperture HA-ADF Detector Understanding the Image includes knowing Detector Geometry Aberration correction increases convergence angle IBF To ELS spectrometer Lupini and Pennycook, Ultramicrosc. 96, (2003), 313.

34. Beam Propagation in Silicon Atomic columns In Amorphous Si PM Voyles, DA Muller, and EJ Kirkland, Microsc. Microanaly. 10 p 291 (2004)

35. Locating the atomic column with the dopant atom can be difficult Column with greater intensity changes. Position of Bi changes from 2 nm depth to 34.2 nm to 75 nm. PM Voyles, DA Muller, and EJ Kirkland, Microsc. Microanaly. 10 p 291 (2004)

36. Localization of ELS Signal Varela, et al., PRL 92, 2004, p 106802 • Localized signal from La in perfect CaTiO3 crystal • Heavy atom in perfect column + beam jumps columns ??? • Imperfect atomic columns + beam jumps columns • Beam spreads from • P column with 0.08 nm slowly varying displacement in InP • Simulates stress at an interface Plamann and Hytch, Ultramicrocopy 96, 2002, p 313. La seen in ELS and STEM image

37. Messages for TEM Community • Decreasing beam diameter still improves images so community needs to continue this effort & We need to further commercialize aberration corrected TEM and STEM • Spread of incident beam from column to adjacent column is partially a result of the horizontal component of momentum (larger convergence angles) in aberration corrected beams. • Thinner Samples give better resolution But • Issue: 10 nm sample thickness is impractical at this time – work on sample prep continues to be important

38. Key Messages for Materials Characterization by TEM • Ability to image atomic columns is critical • Understanding the image is critical • ELS and EDS of atomically localized areas is critical - ouch • Nanotechnology serves as a key means of testing our understanding of imaging and spectroscopy …. and …. Developing materials applications for nanoelectronics • Aberration Correction is the means to solving these problems

39. Acknowledgements • David Bell and his 2003 M&M paper on nanowire TEM • Christian Kiselowski • Dave Muller • Steve Pennycook • Suzanne Stemmer

40. SENSOR based Integrated MetrologyComments on :Advanced Process Control - Advanced Equipment Control • AEC/APC GOAL : model based predictive control based on process and metrology models using in-situ and in-line measurements • Momentum ? • IMA providing its own Roadmap

41. Metrology Questions for Defect and Factory – April 2004 Stresa • What are APC issues for Factory Integration? • “With integrated metrology vs off – line how do you effect control When do you use in-line vs off-line Factory would like to understand if in-situ replaces other metrology or supplements. Common guidelines for - for example - data accessibility -- a usage guideline” • Case for Integrated metrology is made by each IC manufacturer based on its process” • For AEC/APC In addition to Resist Trim CD what other measurements are a priority. • “no” • In track AEC/APC is 3D CD needed. Is it a tool monitor or a real CD metrology.

42. Key Metrology Challenges • Breakthrough microscopy for CD measurement • Measurement capability for control of interface between high  and substrate & gate electrode • Low  killer pore detection and copper void control • Atom by Atom microscopy for materials characterization

43. Will Market Risks allow for innovation?