Metrology Roadmap 2003 Update and ISMT Project Plans

1. Metrology Roadmap2003 Update and ISMT Project Plans Europe Ulrich Mantz (Infineon) could not travel Mauro Vasconi (ST) on phone Japan Yuichiro Yamazaki (Toshiba) Kazuo Nishihagi (Technos) Korea Taiwan US Steve Knight (NIST) Alain Diebold (Int. SEMATECH) Jack Martinez (NIST)

2. AGENDA • 2003 ITRS Changes • Lithography Metrology • FEP Metrology • Interconnect Metrology • Key Challenges

3. Metrology Critical Challenges Five Difficult Challenges ³ 45 nm, Through 2009 • Metrology Integration • Starting Materials and In-line Metrology for strained Si, SiGe, and SOI • Control of high-aspect ratio technologies including copper void detection • Measurement of complex material stacks and interfacial properties • Measurement test structures and reference materials

4. Metrology Critical Challenges Five Difficult Challenges < 45 nm, Beyond 2009 • Nondestructive, production worthy, wafer and mask level microscopy for CD and overlay • New strategy for in-die metrology must reflect across chip and across wafer variation • Statistical limits of sub-45 nm process control • Structural and elemental analysis at device dimensions. i.e. materials characterization • Development of manufacturing metrology when device and interconnect technology remain undefined

5. Practical vs Desired Implementation of P/T • Evaluation of CD measurement capability done using sample with single shape and CD • This misses changes in accuracy and precision due to line edge roughness and sidewall angle, etc. • Propose : Total Measurement Uncertainty (TMU) Defines a new precision (P in the P/T ratio) P(TMU). P(TMU) should be determined on technology representative set of samples that accounts for variations in measurement bias associated with each process level.

6. 2003 ITRS Changes

7. 6.35mm 152mm 152mm EUV Litho Metrology Importance of Mask CD Tables CD Control Starts at the Mask 22 nm Node - 2016 Overlay and CD Control after Exposure 52 nm mask line width 26 nm scattering bars CD Control after Etch 13 nm printed line width 9 nm physical line width

8. Litho Process part of total CD budget • Litho Process range - Litho 2/3 Etch 1/3 in 2002 Litho 4/5 Etch 1/5 in 2003 • Use Process Range for Physical (Etched) Gate for both Printed and Etched Gate • Variances add as sum of squares • Make Precision of Printed gate match that of Etched Gate and Result is that Printed Gate now requires better precision • Statistical Models used by Litho TWG to divide this variation between • Lens Aberration • Reticle CD variation • Inaccurate optical proximity corrections • Illumination effects

9. Dose and focus control errors are largest component of litho CD process range Binary Mask Alt. Phase Shift Mask s1 = mask CD variation R1 = Mask Error factor R2 = Lens Error R3 = Bake Temp DCD/DT  DT R4 = Focus and Dose Variation 90 nm node 65 nm iso lines Sergei Postnikov and Scott Hector: Motorola for Litho TWG

10. Red moved out in Litho Metrology Technology Requirements

11. CD Potential Solutions

12. What are you Measuring? single value from distribution average Distribution of linewidths inside test structure test structure inside a die

13. 3D CD Metrology SEM – Scatterometry – CD-AFM Commercially available R&D Software comparison of top down line scan of edge to golden image Tilt Beam SEM Scatterometry CD-AFM Dual Beam FIB (destructive) Software to convert top down image to 3D image All suppliers appear to offer tilt beam now

14. FEP : High  Metrology • Metal Gate and high k both require metrology development • SOI and Strained Silicon already in initial testing at ISMT • New Transistor Designs being Developed at ISMT

15. Metal Gate impacts selection of Metrology q Models can include interface layer d Phase shift = q 2 d sin l • If Metal Gate is used then either • Integrate metrology with process tool • try X-ray Reflectivity Thanks to Rich Matyi 4 nm HfO2

16. Gaps in Interconnect Metrology • VOID Detection in Copper vias & lines now based on 1/10 via diameter • Barrier/Seed quality on sidewalls • Killer Pore Detection in Low kpore size distribution • Non destructive metrology for adhesion and  (at operating freq.) for patterned wafers

17. Nanowire Transistors and Interconnect 5 nm layer of Ge on top of 4 nm SiOx 10 nm p-Si core diameter & 10 nm i- Ge layer 500 nm L.J. LAUHON, M.S. GUDIKSEN, D. WANG & CHARLES M. LIEBER Nature 420, 57 - 61 (2002)

18. SENSOR based Integrated MetrologyComments on :Advanced Process Control - Advanced Equipment Control • AEC/APC GOAL : model based predictive control based on process and metrology models using in-situ and in-line measurements • Momentum ? • IMA providing its own Roadmap

19. Key Metrology Challenges • Breakthrough microscopy for CD measurement • Measurement capability for control of interface between high  and substrate & gate electrode • Low  killer pore detection and copper void control • Atom by Atom microscopy for materials characterization

20. Will Market Risks allow for innovation?