1 / 18

International Technology Roadmap for Semiconductors Metrology Roadmap 2011

International Technology Roadmap for Semiconductors Metrology Roadmap 2011. Metrology Technical Working Group. Metrology Roadmap 2011. Europe Adrian Kiermasz ( Metryx ) Carlos Beitia ( CEA LETI MINATEC ) Philippe Maillot (ST) Delphine Le Cunff (ST)

melinda-oliver
Download Presentation

International Technology Roadmap for Semiconductors Metrology Roadmap 2011

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. International Technology Roadmap for SemiconductorsMetrology Roadmap2011 Metrology Technical Working Group

  2. Metrology Roadmap 2011 Europe Adrian Kiermasz (Metryx) Carlos Beitia (CEA LETI MINATEC) Philippe Maillot (ST) Delphine Le Cunff (ST) Japan Eiichi Kawamura (Fujitsu Semiconductor) Yuichiro Yamazaki (Toshiba) Masahiko Ikeno (Hitachi High-Tech) Korea Chin Soobok (Samsung) Taiwan North America Yaw Obeng (NIST) Christina Hacker (NIST) George Orji (NIST) Andras Vladar (NIST) Dave Seiler (NIST) Karey Holland (FEI) Scott List (INTEL) Brendan Foran (Aerospace) Ben Bunday (SEMATECH) Vic Vartanian (SEMATECH) Alain Diebold (CNSE – Univ. Albany) - Chair

  3. 200K 20K 2K Metrology/Char. Research Tool Metrology Beta Tool w/precision Metrology Product Tool w/prec. & Uncert. Metrology Alpha Tool 200 20 First Tech. Conf. Device Papers Up to ~12yrs Prior to Product 2 0 24 -96 -72 -24 -48 Metrology Timing Model w/Technology Cycle Timing New for 2010 Production Research Development Process Research Tool Alpha Tool Beta Tool Product Tool Volume (Wafers/Month) 1st 2 Co s Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product Months 2011 2013 2015 2017 2019 2021 Source: 2009 ITRS - Executive Summary Fig 2b

  4. 200K 20K 2K 200 20 First Tech. Conf. Device Papers Up to ~12yrs Prior to Product 2 0 24 -96 -72 -24 -48 Metrology Materials and Test Structure Timing Model w/Technology Cycle Timing New for 2010 Production Research Development Metrology Research Tool Metrology Beta Tool w/precision Metrology Product Tool w/prec. & Uncert. Metrology Alpha Tool Metrology Research Samples Metrology Test Structure Samples @ Man. Design Rules Volume (Wafers/Month) 1st 2 Co s Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product Months 2011 2013 2015 2017 2019 2021 Source: 2009 ITRS - Executive Summary Fig 2b

  5. 2011 Metrology Roadmap

  6. Lithography Metrology Spacers CD-SAXS Contour vs Design Dual Patterning Line Edge Roughness CD Metrology Extendibility MuGFET MuCFET Litho Metrology for 3D Devices Mueller Matrix Ellipsometry

  7. EUV Lithography MetrologyArea of Great Industry Interest Mask Substrate Defect Inspection Mask Blank Inspection Absorber Layer Mo-Si Multi Layer Glass Glass AIMS Patterned Mask Inspection Project what mask will print onto a detector

  8. Direct Self AssemblyMetrology Gap – (3D CD through the structure) Self Assembly Patterning Block co-polymers Black and Bezencenet, IEEE Trans NanoTech 3, (2004) p 412 Stoykovich, et al, Science 308 (2005), 1442

  9. Challenge: Dimensional metrology on complex 3D structures requires many parameters to be measured simultaneously Complex structures such as FinFETs require 3D metrology 12 parameters in diagram, not counting top corner rounding, footing, or etch recess under fin. Gate spacer would increase number of parameters. One example from 2011 SPIE: Fin is measured by CD-SEM or AFM and results fed forward OCD (scatterometry) then simultaneously measures fewer parameters with improved measurement uncertainty and higher speed. All methods are advancing : Complementary metrology delivers better solution gate 1 parameter 3 parameters HM 3 parameters fin HiK/MG 3 parameters 2 parameters gates fins Require measurements of fin CD, height, sidewall angle and roughness.

  10. + III/V and Ge High µAlternative Channel Mat’ls Metrology for FEP EOT & Defects for Alternate Channel Materials Metrology for Generation II and III Metal Gate/High k stacks CD/Sidewall/Height/Stress Metrology for 3D Devices MuGFET MuCFET FDSOI Nano-topography & Local Stress measurements • New Memory Materials • Phase Change Memory

  11. Metrology for FEP Redox memory Where the filaments Start Fiigure Courtesy Brendan Foran, Aerospace corp Tong, et al, IEEE Transactions on Nuclear Science, 57,(2010, p 1640

  12. New Materials impact CD Metrology Optical Properties of next Gen High k wavelength Measuring Interfacial Layer is more challenging TEL – CNSE Collaboration Steve Consiglio/ Rob Clark, GertLeusink TEL / Josh LaRose – CNSE

  13. Metrology for ERM/ERD High carrier mobility and structural robustness have driven a considerable effort in Graphene research Measurement of Bi-layer misorientation Aberration corrected TEM How many Layers? Raman and LEEM Quantum Hall Effect observes the Berry Phase

  14. Metrology for 3D Stacking Overlay – IR Microscopy X-Ray Microscopy 4 3 1 Bonding Defects – SAM Scanning Acoustic Microscopy Stress Metrology Raman Microscopy F)

  15. 3D Metrology - CD-SEM Better CD SEM Via better image acquisition Traditional frame averaging Drift-corrected frame averaging Fast single frame 3D model determines all structure dimensions Andras Vladar, NIST

  16. Modeling, Simulation, and Metrology • Need to connect multiple measurements/methods at nanoscale to properties in a large area using modeling and simulation • Example : Simulations of SRAM cell shows that each transistor experiences a different stress field – measuring one transistor does not represent the entire SRAM Cell I - V Final Stress in SRAM Cell “Sentaurus TCAD simulations from Synopsys – TCAD News Dec 2010”

  17. Metrology Summary 3D Metrology for Advanced Memory • FEP-Interconnect-Litho • USJ Metrology Gap (profile and dose) • PC and STT RAM - New materials for Metrology • Defects in new channel materials • 3D Metrology – Confirm Geometry Requirements e.g. film thickness & properties on sidewall • Reference Methods for 3D Measurements • Composition & Stress – e.g. buried channels • EUV mask metrology requirements • ERD-ERM • STT RAM Transition to FEP & PIDS • Tunnel Dielectric • Magnetic layers and interfaces • Redox RAM • Local characterization of oxygen vacancies • Real device dimensions and structures • Metal filament characterization • Deterministic Doping • Characterize dopants in 3D • Dopant vacancies and interstitials • Directed Self Assembly • Defect detection • Structure variations • Graphene • Defects in CVD Graphene • Mobility & Substrate Interactions • Bandgap Measurement (Strain, etc.) Graphene – C. Kisielowski

  18. Imaging atomic columns & spectroscopy of one atom in column Requirement Aberration Corrected TEM/STEM La seen in ELS and STEM image of CaTiO3 Varela, et al, PRL 92, 2004, p 106802

More Related