Direct Digital Synthesis Theory & Applications

1. Direct Digital Synthesis Theory & Applications 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples paul.smith@analog.com

2. Phase µ Time Fout TIME 360 q = 360t*Fout PHASE 0 TIME

3. Discrete Phase µ Discrete Time Fout TIME 2n-1 PHASE 0 TIME

4. How do you build this? 2n-1 PHASE 0 TIME PHASE ACCUMULATOR n = 24 - 48 BITS n n PHASE REGISTER n 1 CLOCK Fclk

5. DELTA PHASE REGISTER M n M FREQUENCY CONTROL M = TUNING WORD Changing Frequency 2n-1 PHASE 0 TIME PHASE ACCUMULATOR n = 24 - 48 BITS n n PHASE REGISTER n M CLOCK Fclk

6. Getting a Sinewave Output AMPLITUDE 0 TIME PHASE ACCUMULATOR n = 24 - 48 BITS n DELTA PHASE REGISTER M n n PHASE REGISTER n p PHASE-TO AMPLITUDE CONVERTER M CLOCK FREQUENCY CONTROL M = TUNING WORD Fclk

7. Signal Flow Through the DDS Architecture F clk M F = o n 2 REFERENCE CLOCK F clk DDS CIRCUITRY (NCO) TO n N PHASE FILTER PHASE - TO - AMPLITUDE M ACCUMULATOR DAC CONVERTER (n - BITS) TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REFERENCE CLOCK FREQUENCY DIGITAL DOMAIN ANALOG

8. 31 29 … … 4 2 0 Another Way to Look at DDS vector data raw DDS-DAC output filtered output compared output … 6-bit phase wheel 4 3 2 1 0 63 5-bit amplitude resolution …

9. Direct Digital Synthesis Theory & Applications 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples paul.smith@analog.com

10. PHASE TRUNCATION 12-19 BITS AMPLITUDE QUANTIZATION DAC DAC ERRORS Errors in a DDS System PHASE ACCUMULATOR n = 24 - 48 BITS n n DELTA PHASE REGISTER M n n PHASE REGISTER n p PHASE-TO AMPLITUDE CONVERTER M CLOCK FREQUENCY CONTROL M = TUNING WORD N-BITS (10-14) F clk SYSTEM CLOCK F out

11. Amplitude Errors • Quantized waveform ≠ Sinewave • Therefore there will be spectral components • 6.02N + 1.76 quantization noise is only valid when clock and data are uncorrelated. NOT THE CASE for a DDS! • DAC non-linearities • INL and DNL spurs will alias • Harmonics from the analog output stage will NOT alias

12. Distortion in an analog system Distortion in an sampled system Freq Fs 2Fs All the distortion terms show up in the passband Aliased Distortion Terms Freq

13. Effects of Choosing an Odd Value For M 2n-1 M=4 PHASE 0 TIME 2n-1 31 30 30 29 28 27 M=5 PHASE 0 TIME

14. Effect Sampling Clock / Output FrequencyRatio on SFDR for Ideal 12-bit DAC (A) FOUT = 2.0000 MHz, fS = 80.0000 MHz (B) FOUT = 2.0117 MHz, fS = 80.0000 MHz SFDR = 77dBc SFDR = 94dBc Ratio = 80/2 = 40 Ratio = 80/2.0117 = 103/4096 FFT SIZE = 8192 THEORETICAL 12-BIT SNR = 74dB FFT PROCESS GAIN = 36dB = 10log(8192/2) FFT NOISE FLOOR = 110dBFS

15. Phase Truncation Errors • Green points (outer circle) show n=8 phase accumulator • 256 phase steps • M=6 in this illustration • Red points (inner circle) show p=5 • 32 steps passed on the phase-amplitude converter • 3 points get truncated, but the 1st and 4th do not • As the phase moves around the circle, the error becomes periodic • Phase error = Amplitude error • Due to phase-amplitude converter • Periodic phase error = periodic amplitude error = spectral component

16. Phase Truncation Error (Time Domain) • Not only is the error periodic, but it also has a ramp shape • Therefore we expect the spectral components fall at a 1/m rate (m = harmonic number)

17. Phase Truncation Error (Frequency Domain) • However, since this is a phenomenon in the digital domain, these spurs will alias. • The largest spur is approximately -6.02p dBc • (e.g., -72 dBc for p=12)

18. Direct Digital Synthesis Theory & Applications 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples paul.smith@analog.com

19. Additional DDS Capabilities • Add Frequency Register • Sweep • Chirp • RAM profiles • Amplitude control • IQ modulation • Multi-DDS • For arrays • Phase offset/compensation • Spurkiller

20. PRE-PROGRAMMED FREQUENCY CONTROL or RAM FREQUENCY TIME Frequency Control PHASE ACCUMULATOR n = 24 - 48 BITS n DELTA PHASE REGISTER M n n PHASE REGISTER n p PHASE-TO AMPLITUDE CONVERTER M CLOCK FREQUENCY CONTROL M = TUNING WORD Fclk

21. AMPLITUDE REGISTER DAC Amplitude Control PHASE ACCUMULATOR n n PHASE REGISTER n p PHASE-TO AMPLITUDE CONVERTER M CLOCK Fclk

22. IQ Modulation • The DDS is the LO for the Quadrature Modulator • Everything is in the Digital Domain and can be made as perfect as necessary by adding more bits • Upsampling gives the DDS room to move the signal around

23. Multiple DDS • Precise phase control allows use in beam forming systems • Each DDS starts up in its own phase • Phase offsets compensate for phase mismatch in analog reconstruction filters

24. SpurKiller Technology • Use an auxiliary DDS channel to add in a signal at the same frequency and amplitude as the spur, but 180° out of phase with the highest spur… DDS Channel for spur reduction Phase Offset Frequency S Accumulator S DAC COS(X) FTW 10 16 14 32 AD9911 DDS core DDS Channel DDS Channel for phase for amplitude Register Register modulation modulation Register

25. AD9911 SpurKiller 500 MHz DDS It’s all in the Digital Domain!

26. The Results of Using SpurKiller Technologyon a DDS Output Spur BEFORE AFTER 500 kHz / DIVISION 500 kHz / DIVISION OUTPUT FREQUENCY = 166 MHz Fclk = 500 MSPS

27. Direct Digital Synthesis Theory & Applications 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples paul.smith@analog.com

28. Output Circuits IFS – I IOUT ROUT ROUT I IOUT RSET • IFS 2 - 20mA typical • ROUT > 100k • Output compliance voltage < ±1V for best performance • That is, the output can go below ground!

29. Single Transformer Coupling MINI-CIRCUITS ADT1-1WT 1:1 LC FILTER VLOAD = ± 0.333V 0 TO 20mA IOUT +0.45dBm 50 RLOAD = 50 CMOS DAC ± 6.67mA IOUT 20 TO 0mA 50 Note: The 100 differential primary driving impedance represents the best compromise between the effects of transformer impedance mismatch and DAC SNR performance.

30. Dual Transformer Coupling VLOAD = ± 0.333V 0 TO 20mA +0.45dBm TO 50 LOAD CMOS DAC 50 W 20 TO 0mA Mini-Circuits Coilcraft 50 W ADTL1-12 TTWB-1-B 20-1200MHz 0.13-425MHz • Transmission Line Transformer in series with outputs to help cancel HD2 • Dual Transformer design helps minimize imbalance caused by mis-matched signal coupling from primary to secondary windings. • RF Transformer from Coilcraft (TTWB-1-B) shows better performance for IFs at 200-300 MHz

31. Differential DC Coupling Using a Dual-Supply Op Amp 1000 0 TO 20mA 500 +5V 0V TO +0.5V – IOUT ± 1V 25 AD8055 CMOS DAC CFILTER + OR AD8021 –5V 500 IOUT 20 TO 0mA +0.5V TO 0V 25 1000 1 2 • 50 • CFILTER f3dB =

32. Differential DC Coupling Usinga Single-Supply Op Amp 1k 0 TO 20mA 500 +5V 0V TO +0.5V +2.5V – IOUT ± 1V 25 AD8061 CMOS DAC CFILTER + 500 IOUT +5V 20 TO 0mA 2k +0.5V TO 0V 25 2k 1 2 • 50 • CFILTER f3dB =

33. High-Speed Buffered Differential DAC Outputs 2.49k 0 TO 20mA 500 0V TO +0.5V + IOUT 25 VOCM AD813x ADA493x CMOS DAC CFILTER 500 5V p-p DIFFERENTIAL OUTPUT IOUT – 20 TO 0mA 2.49k +0.5V TO 0V 25 1 2 • 50 • CFILTER f3dB =

34. Generating a Clock With a DDS • External filtering removes unwanted images • A squaring circuit converts the signal back to a digital clock

35. Why You Need a Reconstruction Filter • Fout = 56 MHz, Fclk = 175 MHz • The MSB does not have a consistent pulse width • Jitter shows up when unfiltered output is fed directly to a comparator

36. AN-823 Discusses DDS-based Clocks With Very Low Phase Noise REF CLOCK = 500MHz, MULTIPLIER DISABLED 100.3 MHz 75.1 MHz 40.1 MHz 15.1 MHz 15.1 MHz 40.1 MHz 75.1 MHz 100.3 MHz Phase noise floor below –150dBc/Hz Power dissipation <200mW per channel

37. AD9858 1GSPS DDSwith Phase Detector and RF Mixer

38. Phase/ Frequency Detector Loop Filter VCO Fref RF ÷N PLL General Architecture = F N F RF ref

39. DDS Used as PLL Reference Phase/ Frequency Detector Loop Filter VCO Fref DDS RF ÷N M F = ref F NM RF n 2

40. n 2 DDS Used in Fractional-N Loop Phase/ Frequency Detector Loop Filter VCO Fref RF DDS M F = ref F RF M

41. F clk n 2 DDS Used in Translation Loop Phase/ Frequency Detector Loop Filter VCO Fref RF ÷N DDS Fclk + = F N F M RF ref

42. PA BPF BPF BPF RF Upconversion Using Analog IQ Mixing ADL537x RF TxDAC I I DSP CHANNEL FILTER  0° AD977x LO 90° Q Q TxDAC 300MHz – 3.8GHz

43. PA BPF BPF N N RF Upconversion Using Digital IQ Mixing QDUC = QUADRATURE DIGITAL UPCONVERTER IF TO 400MHz (AD9957) RF AD9857 AD9957 I I DSP CHANNEL FILTER DAC  0° NCO 90° Q Q LO

44. PA BPF BPF BPF RF Upconversion Using Dual DDS for LO ADL5385 RF TxDAC I I 0° DSP DUAL DDS CHANNEL FILTER  AD977x 90° Q Q TxDAC 50MHz - 2.2GHz

45. On-Line DDS ToolsADIsimDDS

46. DDS Design Tool Main Screen

47. DDS Design Tool: Tabular Display of Spurs

48. DDS Design Tool: Display Options and Filter Selection

49. Click ‘More …’ to find the cool technical papers http://www.analog.com/dds

50. Summary • DDS can be used to obtain a variety of precision waveforms • Compared to other frequency generating techniques, a DDS has the following advantages: • Precise phase control without affecting frequency • Precise frequency control without affecting phase • Fast arbitrary phase changes • Fast arbitrary frequency changes • Precision modulation • DDS has well known error characteristics • Care must be taken designing the output analog circuitry • Applications abound! ADI makes some GREAT parts