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DSP Systems Implementation Course Seminar

DSP Systems Implementation Course Seminar. Tehran University Electrical And Computer Engineering Department Spring 2004. A Practical Example Of DSP System Design, ADSL Modem DMT Engine. Outline. A Glance At ADSL Modems Structure Digital System Design Methodology Design Flow

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DSP Systems Implementation Course Seminar

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  1. DSP Systems Implementation Course Seminar Tehran University Electrical And Computer Engineering Department Spring 2004

  2. A Practical Example Of DSP System Design, ADSL Modem DMT Engine DSP Systems Implementation

  3. Outline • A Glance At ADSL Modems Structure • Digital System Design Methodology • Design Flow • Finite Precision Arithmetic Libraries • ADSL Modulator/Demodulator Design • ADSL Time Equalizer Design DSP Systems Implementation

  4. A Glance At ADSL Modems StructureADSL Modem Modulation • Discrete Multi Tone (DMT) Modulation • Simple Digital Implementation By FFT, IFFT • Uses FDM • 256 Sub-Channels • QAM In All Channels • Simultaneous Voice Transmission DSP Systems Implementation

  5. A Glance At ADSL Modems StructureADSL Modem Block Diagram • ADSL DMT Engine Block Diagram DSP Systems Implementation

  6. Digital System Design MethodologyDesign Flow- All Steps Together • General Methodology • Much Human Brain Work • Less Automatic Procedures • Test & Verification Importance DSP Systems Implementation

  7. Digital System Design MethodologyDesign Flow Step One: Simulation • High Precision Modeling • Using C Or MATLAB • Converting High Level Protocol Or Standard To A Software Model • System Environment Modeling • Engineering Modeling • Quantization Noise And Other Finite Precision Effects Modeling • Parametric Modeling To Find Noise-Parameter(s) relations • Wide Simulation And Parameter Extraction DSP Systems Implementation

  8. Digital System Design MethodologyDesign Flow Step One: Simulation- Important Notes • For High Precision Modeling: • “MATLAB” Is Preferred Because Of Its Friendly Interfaces, Ready Modules And Visual Capabilities • “C” Is Preferred Because Of Its High Simulation Speed • For None-Ideal Engineering Modeling • Finite-Precision-Arithmetic Libraries • Fixed-Floating Point Support • Different Round-Off, Saturation, … Strategies Support DSP Systems Implementation

  9. Digital System Design MethodologyDesign Flow Step One: Simulation- Important Notes • Common Parameter Extraction Method • Finding (Output Error- Parameter(s)) Curves Using The Below Scheme • Common Output Error Criterions: BER, SNR And MSE • Finding Optimal Point On The Curve(s) To Satisfy Defined Error Conditions With The Lowest Possible Cost DSP Systems Implementation

  10. Digital System Design MethodologyDesign Flow Step Two: Hardware Modeling • Golden Model Creation • For Test Purpose • Behavioral Modeling • Component Modeling • Interfacing Considerations • Model Synthesizability • Structural Modeling • System Modeling • Components Wiring DSP Systems Implementation

  11. Digital System Design MethodologyDesign Flow Step Two: Hardware Modeling- Important Notes • Golden Model Creation • Simplifies Test Of The Final Model • Functionally Same As C Or MATLAB Model • Not Necessarily Synthesizable Or Efficient • Component Modeling • Common Design Strategy: Top-Down Design, Bottom-Up wiring • Extracted Parameters From Simulation Step, Inserted Into Components DSP Systems Implementation

  12. Digital System Design MethodologyDesign Flow Step Three: Implementation • FPGA Implementation • FPGA Specific HDL Languages Such As AHDL • Usually Better Performance When Lower Level Components Described @ RTL Level • Hardware Emulation Systems • ASIC Implementation DSP Systems Implementation

  13. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C Does Not Have Sufficient Capabilities Needed For Bit-True Modeling • Special Libraries Need To Be Developed That Support • Different Finite-Length Number Representations (Fixed, Float,…) • Different Finite-Length Sign Representations (2’s Complement, Sign And Magnitude, …) • Basic Arithmetic Operations With Finite Precision (Sum, Sub,…) • Different Round-Off Strategies (Truncation, Rounding,…) • Different Overflow Strategies (Maximum Saturation, Zero Saturation, Wrap Around,…) DSP Systems Implementation

  14. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Using The Libraries, The System Should Be Modeled And Simulated With Different Library Options • All Trade-Offs And Strategies Are Extracted • Number Representation Method (Fixed, Float, …) • Sign Representation • Round-Off Strategy • Overflow Strategy • Each Trade-Off Or Strategy Corresponds To A Different Hardware Implementation DSP Systems Implementation

  15. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • “ACOLADE” Library • C Language • Parameters • Word_width (Fixed Or Float Selection) • Precision (Precision Selection) • RND_CHR (Round-Off Strategy) • OVL_CHR (Overflow Strategy) DSP Systems Implementation

  16. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • CFinite Length Arithmetic Modeling Extension, C_FLAME Library • Developed In UT VLSI Lab • Support Truncation And Rounding Round-Off Strategies • Library Interface Functions: Dec2bin, Bin2dec • Negation Function: Negate DSP Systems Implementation

  17. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • CFinite Length Arithmetic Modeling Extension (C_FLAME) Library • Arithmetic Functions • Fixed Point • Scaling Functions: Sum, Sub, Sum_wa, Multiply • Saturation Functions: Sum_sat, Sub_sat, Sub_wa • Block Floating Point • Sum_bfp, Sub_bfp • Special Purpose Function: Multiply_ideal DSP Systems Implementation

  18. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C_FLAME Library Data Structure • High precision input data for library must be scaled, -1≤ Inputs < 1 • Fixed point is aligned after the most significant bit of the numbers (MSB of each number, represents sign) • High precision scaled input data should be converted to finite precision data for C_FLAME functions by library interface functions DSP Systems Implementation

  19. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C_FLAME Library Data Structure (Cntd.) • Inside C_FLAME, all binary finite precision numbers treated as integer numbers • Numbers representation inside C_FLAME struct binary{ long int number; int length;} DSP Systems Implementation

  20. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Example of input preparation for C_FLAME library • r1=0.625; r2=0.9999; r3=-1; //Real Input Data To Library • Int Wordlength=8; //Determining Finite Precision • Struct binary b1,b2,b3; //Library Internal Data Structures • //void dec2bin(double a, int wordlength, binary *num) • Dec2bin(r1,wordlength,&b1); //b1={ 80 , 8 } 80=(0101,0000) • Dec2bin(r2,wordlength,&b2); //b2={ 127 , 8 } 127=(0111,1111) • Dec2bin(r3,wordlength,&b3); //b3={ 128 , 8 } 128=(1000,0000) DSP Systems Implementation

  21. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Another example of data manipulation by C_FLAME library functions • r1=0.65625; //Real Input Data • Int Wordlength=8; //Determining Finite Precision • Struct Binary b; //library Internal data structure • Dec2bin(r1,wordlength,b); // b= { 84 , 8 } 84 =(0101,0100) • Negate(&b) // b= { 172, 8 } 172=(1010,1100) DSP Systems Implementation

  22. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Different C_FLAME Summation Functions • Saturated Fixed Point Summation • Void Sum_Sat (binary a, binary b, binary *k) • Scaling Fixed Point Summation • Void Sum (int round_truncate, binary a, binary b, int resultlength, binary *k) • Block Floating Point Summation • void Sum_bfp(int round_truncate, binary a, binary b, int resultlength, binary *k) • Wrap Around Summation • Void Sum_wa(binary a, binary b, binary *k); DSP Systems Implementation

  23. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different Add functions in C_FLAME library • Sum_sat Function • Output length=input length • No round-off strategy needed • When Not Overflow The function returns Result(N-1 ,0) • When Overflow The function saturates and returns Maximum and minimum representable numbers DSP Systems Implementation

  24. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different Add functions in C_FLAME library • Sum Function • If Output length=input length +1 function returns (C & Result(N-1,0)) Round-off strategy not needed • If output length= input length function returns (C & Result(N-1,1)) considering round-off strategy DSP Systems Implementation

  25. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different Add functions in C_FLAME library • Sum_bfp Function • If Output length=input length +1 function returns (C & Result(N-1,0)) Round-off strategy not needed • If output length= input length • When Not Overflow function returns (Result(N-1,0)) • When Overflow function returns (C & Result(N-1,1)) DSP Systems Implementation

  26. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different Add functions in C_FLAME library • Sum_wa Function • Output length=input length • No round-off strategy needed • No Saturation Strategy DSP Systems Implementation

  27. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • A finite precision complex multiply Finite_precision_complex_multiply (double: Ra,Ia,Rb,Ib, int r_t) { Struct Binary: Rab,Iab,Rbb,Ibb,partialmul1,partialmul2; dec2bin(Ra,8,Rab); dec2bin(Ia,8,Iab); dec2bin(Rb,8,Rbb); dec2bin(Ib,8,Ibb); Multiply(r_t , Rab , Rbb , 8 , &Partialmul1); Multiply(r_t , Iab , Ibb , 8 , &Partialmul2); sub(r_t , partialmul1 , partialmul2 , 9 , &resultreal); Multiply(r_t , Rab , Ibb , 8 , &Partialmul1); Multiply(r_t , Iab , Rbb , 8 , &Partialmul2); sum(r_t , partialmul1 , partialmul2 , 9 , &resultimag); realpart=bin2dec(resultreal); imagpart=bin2dec(resultimag);} DSP Systems Implementation

  28. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Block Floating Point • Extra Hardware • A Solution Between Fixed And Floating Point • Wide range Representation Capability • Simple Hardware Implementation • Low Quantization Noise Sensitivity • Low Delay DSP Systems Implementation

  29. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Example Of C Finite Length Arithmetic Modeling Extension (C_FLAME) Library Functions • Block Floating Point Illustration DSP Systems Implementation

  30. Digital System Design MethodologyADSL Modulator/Demodulator Design • IFFT/FFT Used For Modulation/Demodulation • The Most Complicated And Most Important Block Of An ADSL Modem • Hardware Structure • Operation Count • Quantization Noise • Design Constraints (Speed, Area, Power) DSP Systems Implementation

  31. Digital System Design MethodologyADSL Mo/Dem- Implementation Method Selection Space • A Multi-Dimensional Space • Different Algorithms • Radix 2, Radix 4, Radix 8, Split Radix, Mixed Radix • Different Algorithm Versions • Decimation In Time (DIT), Decimation In Frequency (DIF) • Different Butterfly Structures • Symmetric Structures, Asymmetric Structures • Different Implementations • Full Parallel Structure, Column Structure, FFT Processor Structure, Pipeline Structure DSP Systems Implementation

  32. Digital System Design MethodologyADSL Mo/Dem- Choosing Suitable Structure • Selection Criteria • Maximum Delay Constraint (250 µs) • Hardware Cost (# of Adders, Multipliers,…) • Maximum Quantization Noise Acceptable • Implementation Complexity (VLSI Layout,…) DSP Systems Implementation

  33. Digital System Design MethodologyADSL Mo/Dem- Choosing Suitable Structure • So Many Trade-Offs Must Be Considered And Resolved • # Of Operations (~Quantization Noise Error) • Register Word Lengths • Butterfly Hardware Complexity • Symmetric Or Asymmetric Butterfly Hardware • Delay • Hardware Component Count • Hardware Utilization • Input Output Sequence • Final Chip Size DSP Systems Implementation

  34. Digital System Design MethodologyADSL Mo/Dem- Choosing Suitable Structure • Important Results Of Browsing Selection Space • Result#1: Hardware Complexity Decreases as the Radix Increases ! • Result#2: Operations Count Decreases as the Radix Increases! • Result#3: Mixed-Radix Algorithms are Hardware Optimized Solutions! • Result#4: Implementation Complexity Increases as the Radix Increases (More Than 4 or 8)! • Result#5: Hardware Utilization Decreases as the Radix Increases (Generally)! DSP Systems Implementation

  35. Digital System Design MethodologyADSL Mo/Dem- The Chosen Algorithm • Mixed-Radix 2^2 +2 Algorithm • Hardware Complexity of Radix-4 Algorithms! • Operation Count of Radix-4 Algorithms! • Mixed-Radix Hardware Optimized With a Very Simple Controller! • Implementation Complexity of Radix-2 Algorithms! • Hardware Utilization of Radix-2 Algorithms! DSP Systems Implementation

  36. Digital System Design MethodologyADSL Mo/Dem- The Chosen Algorithm • Mixed-Radix 2^2 +2 Algorithm DFG DSP Systems Implementation

  37. Digital System Design MethodologyADSL Mo/Dem- The Selected Implementation Method • Different Implementations • Fully Parallel FFTs • Column FFTs • Pipeline FFTs • FFT Processors • The Selected Implementation Method • Pipeline FFT Implementation DSP Systems Implementation

  38. Word Length=12 0.16 Word Length=16 0.04 0.15 0.14 0.03 Error 0.13 Error 0.02 0.12 0.01 0.11 8 10 12 14 16 Constant Length 0 8 10 12 14 16 Constant Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change Of “Output Error” Due To Increase Of “Constant Length” DSP Systems Implementation

  39. Constant Length=12 20 15 Error 10 Constant Length=16 20 5 15 0 8 10 12 14 16 Error Word Length 10 5 0 8 10 12 14 16 Word Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change Of “Output Error” Due To Increase Of “Word Length” DSP Systems Implementation

  40. Constant Length=8 16 14 12 Constant Length=16 10 16 Truncation Error 8 14 6 12 4 10 Rounding Truncation 2 Error 8 0 8 9 10 11 12 13 14 15 16 6 Word Length 4 Rounding 2 0 8 9 10 11 12 13 14 15 16 Word Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change Of “Output Error” Due To Using “Rounding” Instead Of “Truncation” DSP Systems Implementation

  41. Digital System Design MethodologyADSL Mo/Dem- Components Implementation • Butterfly Structures Of The Algorithm BF I BF II DSP Systems Implementation

  42. Digital System Design MethodologyADSL Mo/Dem- Components Implementation • Design Multipliers Enhancement To Do Rounding Instead Of Truncation On Output DSP Systems Implementation

  43. Digital System Design MethodologyADSL Mo/Dem- Components Implementation • Design Adders/Subtractors Enhancement To Do Unbiased Rounding Instead Of Truncation On Output DSP Systems Implementation

  44. Digital System Design MethodologyADSL Time Equalizer Design • A Digital Filter To Cancel Line Distortion • Implemented As A 16 Tap Adaptive FIR Filter (Changeable Coefficients) DSP Systems Implementation

  45. Digital System Design MethodologyADSL Time Equalizer - Choosing A Suitable Structure • Constant Length = Filter Word Length • Selection Criteria • Maximum Delay Constraint • Hardware Cost (# Of Adders, Multipliers, …) DSP Systems Implementation

  46. FIR Filter Output Error 0 . 045 0 . 04 0 . 035 0 . 03 Error 0 . 025 0 . 02 0 . 015 0 . 01 0 . 005 0 8 9 10 11 12 13 14 15 16 Word Length Digital System Design MethodologyADSL Time Equalizer – TEq C Simulation Results • Change Of “Output Error” Due To Increase Of “Word Length” • Output Error Is Negligible With Respect To FFT DSP Systems Implementation

  47. FIR Filter Output Error 0.045 0.04 0.035 0.03 Error 0.025 Truncating 0.02 0.015 0.01 Rounding 0.005 0 8 9 10 11 12 13 14 15 16 Word-Length Digital System Design MethodologyADSL Time Equalizer – TEq C Simulation Results • Change Of “Output Error” Due To Using “Rounding” Instead Of “Truncation” DSP Systems Implementation

  48. Digital System Design MethodologyADSL Time Equalizer – Implementation • Block Floating Point Method DSP Systems Implementation

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