Project Final Semester A Presentation

1. Project Final Semester A Presentation 03.2011 Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri YavichAlon • Guided by – Porian Moshe

2. Reminder Gym Control Room Gym Compressed data (Wireless) ❤ ❤ 142 132 ❤ ❤ 170 79 ❤ ❤ 130 127

3. TOP architecture

4. FPGA – Cyclone II Packet TX Host Matlab RAM MUX Message Encoder UART TX TX 115,200KBit/sec REGISTERS RX Packet RX UART RX DEC RAM Message Decoder Sync Resets Global Nets Ext. Clk Mem Write CRC Ext. Reset Clocks Mem Read Arbiter VGA Display Display Controller SDRAM Controller RunLen Decoder IS42S16400 SDRAM VESA 800x600 Implemented, not integrated Done Not Implemented Update Required

5. Micro architecture

6. VGA Display Matlab CRC_ERR VALID Line legend MSG_OK 1 bit 40MHz VALID REQ Message Decoder RAM Controller 8 bits RD_adress 10 bits 16 bits n_pix RGB 22 bits Display Controller WR_addr WREN DATA Num Pixels 40MHz RAM UART UART RXD UART RXP REG Controller DATA EN DATA DATA FIFO (dual clock) Data&Valid UART TXD from UART TX REQ DEC CheckSum & Valid CheckSum TYPE REG Addr REG Len REG Type COL_EN COLOR CRC_ERR FROM MSG_DEC RunLen Decoder DATA DATA REGISTERS MP REGS CRC Status REG CRC STATUS RX_RDY to MEM READ DATA DATA_RDY from MEM READ REQ Mem Write RESET Status EN UART TXD to UART TX REP RX_RDY from MEM READ DATA_RDY to MEM READ Addr SDARM ACK DATA REQ SDRAM Controller COLOR UART TXP DATA Arbiter Mem Read Data & Control Data & Control EMPTY REQ REQ VALID ACK TX PACK FIFO DATA & Valid 50MHZ DATA 40MHZ (VESA) Adress Global Nets 133MHZ (SDRAM) VALID REQ Reset Sync Resets FULL

7. New Implemented IPs Global Nets

8. New Implemented IPs Global Nets • Global Nets • Reset Filter

9. New Implemented IPs Global Nets • Global Nets • Sync Reset Generator 133MHz / 40MHz Sync Reset De-activation 50MHz

10. New Implemented IPs Global Nets • Global Nets • Wave

11. New Implemented IPs VESA Generator • VESA Generator: • Supports any kind of resolution and timing (Set by generic parameters) • Inputs: • R, G, B (Generic size for each) • Frames sizes (Wraps the image) • Handshake with data provider • Outputs: • R, G, B • Hsync, Vsync, Blank signals • Handshake with Data Provider

12. New Implemented IPs VESA Generator • VESA Generator: • Pinout Handshake RGB(from Data Provider) RGB Frame Parameters Sync, Blank Enables Handshake

13. New Implemented IPs VESA Generator • VESA Generator: • Pipeline, for supporting greater clock frequencies

14. New Implemented IPs VESA Generator • VESA Generator: • Pipeline, for supporting greater clock frequencies

15. VESA Test Bench Image Frame RGB RGB Image Data Provider Image Collector VESA Generator (DUT) VSync Frames Sizes HSync Enables Blank Handshake This will be shown using VGA and DE2 board

16. VESA Test Bench • Output Examples Frame

17. Maximum Current Project’s Frequency • 163MHz. UART RX is the slowest component. Signal route through FPGA Logic Pin

18. Improvements done from last presentation • UART Rx • Data is being collected to Shift Register • Message Packs: • Data is being collected and transmitted using Shift Register. • Maximum frequency improved from 150MHz to 180MHz

19. New Implemented Simulation Models • VESA Image Generator • Transmits an image from file, with different image’s parameters, and different frames sizes • VESA Image Collector • Collects transmitted images, and store them to file

20. Documentations • Done: • SDRAM Controller * • UART RX, TX • MessagePack + Checksum • VESA • Clocks and Resets • Documentation Example: VESA

21. Conclusions • 2 FF for every a synchronized input FPGA pin is essential, to prevent metastability from entering the system. • Using Shift Register makes the design to work in greater clock frequency. • Pipeline can improve performance. • RTL view can teach a lot: RAM can be implemented in many ways, and only RTL can show what is the correct way.

22. Conclusions (Cont.) • Synchronizing the reset negation to the clock’s rising edge is essential, to prevent metastability from entering the system.

23. Conclusions (Cont.) • Organized working methods saves time: • SVN – Difference between previous versions • Code Review – Improves our knowledge • Documentations – Causes to understand better what we are doing • Comprehensive SIMULATIONS – It is much easier to find bugs in simulation than in the lab  S A V E S T I M E!!!

24. Schedule Done Done Done Done Done Partial Done Done Done

25. Schedule Done Done Now

26. Schedule