1 / 74

Final A Project Presentation

Technion – Israel Institute Of Technology Electrical Engineering Department. High speed digital systems laboratory. Final A Project Presentation. Real Time Image Processing Presented by: Baruch Koren Shahaf Fisher. Instructor: Mr. Almog Assaf. Technion – Israel Institute Of Technology

marlin
Download Presentation

Final A Project Presentation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Final A Project Presentation Real Time Image Processing Presented by: Baruch Koren Shahaf Fisher Instructor: Mr. Almog Assaf

  2. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Agenda • Project’s Goals. • System Block Diagram and System overview. • Defining DVI interfaces and generic blocks. • Image Processing Background. • Development Stages in designing the Generic Space Converter. • Validation using Matlab and Modelsim simulator. • Integration & Implementation in the gidel ProcWizard system. • Demonstration – Real Time Image Processing

  3. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Project’s Goals • Preparing a systematic infrastructure for future laboratories projects. • Preparing instructions for integrating new components to this system. • Studying this complex system - the environment and the designing tools. • Studying VHDL language, with an emphasis on coding style, modular and generic design.

  4. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Project’s Goals • Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems.

  5. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  6. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Overview • System Clocks. • DVI interfaces. • Generic modules. • Gidel interface. • Space converters

  7. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs and PLLs • Input Clocks: • Main clock (clk0,clk1). • Local bus clock (lclk). • Slower clock (clk2). • System PLLs: • pll4ddr2. • user_pll.

  8. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs and PLLs

  9. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs and PLLs

  10. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  11. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  12. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory DVI interfaces Local Bus External ddrII Memory interface ck_a ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  13. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory DVI interfaces • Connection between the DVI Reciever and Transmitter to the FPGA’s top level hierarchy. • Settings for using default DVI Receiver (SiI1171) operation mode: • not programmable - with no I2C involve • 24-bit pixel data for one pixel per clock • Settings for using default DVI Transmitter (SiI1172) operation mode: • not programmable - with no I2C involve. • samples one-half pixel (12 bit) at every latch falling and rising edge of the clock.

  14. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory 12bit 24bit Before DVI interfaces CLK idck_tx odck_rx RX TX data_tx qe_rx de_tx de_rx hsync_rx hsync_tx vsync_rx vsync_tx DVI Output i2c and control i2c and control DVI input

  15. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory After DVI interfaces idck_tx odck_rx RX TX data_tx qe_rx 24bit 24bit 24bit 12bit de_tx de_rx hsync_rx hsync_tx vsync_rx vsync_tx DVI_interface_2rx DVI_interface_2tx i2c and control i2c and control DVI input DVI Output

  16. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  17. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Generic modules • Generic block type 1 • Generic block type 2

  18. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Defining Generic block type 1 Clk data_in(23 DOWNTO 0) data_out(23 DOWNTO 0) data_en_in data_en_out 1 hsync_in hsync_out vsync_in vsync_out

  19. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Integrating Generic block type 1 idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_in data_out 24bit 24bit 24bit 12bit data_en_in 1 data_en_out de_tx de_rx hsync_in hsync_rx hsync_out hsync_tx vsync_rx vsync_tx vsync_in vsync_out DVI_interface_2rx block1 DVI_interface_2tx DVI Output i2c and control i2c and control DVI input

  20. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Defining Generic block type 2 Clk Clk data_in data_out data_in data_out syncs_in syncs_out syncs_in syncs_out 2 2 Write_en read_en Write_en Write_en read_req Write_req Write_req Write_req Controller

  21. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory • Till here we prepared all of the infrastructure for us and for future laboratory projects. • From here we will design the Generic Space Converter.

  22. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  23. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Color Spaces-RGB RGB model uses three numerical components to represent a color in a three-dimensional Cartesian coordinate system. Each component has a range of 0 to 255 (for a 8-bit representation per color).

  24. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Color Spaces-RGB RGB is an additive color system. Incompatibility of RGB space to Image Processing: • processing an image in the RGB space is more complex. • Using RGB requires wider bandwidth and larger storage space. If we use a color space which does a separation between intensity component and chrominance components: • Image processing algorithms will be faster, demand less bandwidth and less storage space,andcheaper.

  25. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Color Spaces-YCbCr The YCbCr is a model which does a separation between intensity (luma) component (Y) and chrominance components (Cb,Cr).

  26. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Color Spaces - RGB  YCbCr The basic equations to convert between gamma-corrected RGB (notated as R’G’B’) and YCbCr are:

  27. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Designing Generic Space Converter – Generic block type 1

  28. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Accuracy (Generic): • X_in, Y_in, Z_in: Default unsigned 8.0 bits. • X_out, Y_out, Z_out: Default unsigned 8.0 bits. • X_offset, Y_offset, Z_offset, b_i: Default size s9.0 bits, when s stand for sign bit. • a_ij : Default size s2.10 bits, when s stand for sign bit. note: • Output size need to be at the same size as input size.

  29. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  30. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Designing the generic Space Converter – Bottom Up Design input 8bit S10.0 bit sum offset output S9.0bit mult S12.10 bit a_ij S2.10 bit sum_mult

  31. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Designing the generic Space Converter – Bottom Up Design b_1 S9.0bit X_in 8bit X_offset S9.0bit S12.10 bit a_11 S2.10bit sum_mult Y_in 8bit clipping X_out Y_offset S12.10 bit S9.0bit a_12 8 bit S2.10bit S14.10 bit S15.10 bit sum_mult Z_in 8bit Z_offset S9.0bit a_13 S2.10bit S12.10 bit sum_mult gen_space_conv_1_component

  32. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Designing the generic Space Converter – Bottom Up Design X_in bypass Y_in Z_in X_out X_offset Y_offset Z_offset a_11 gen_space_conv_1_component a_12 Y_out a_13 … a_31 gen_space_conv_1_component a_32 a_33 Z_out b_1 b_2 gen_space_conv_1_component b_3 generic_space_conv

  33. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  34. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  35. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  36. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Image file Image file MATLAB coding of RGB2YCbCr converter main RGB 2 YCbCr read file write file

  37. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory MATLAB RGB2YCbCR result RGB image YCbCr image

  38. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Coding

  39. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  40. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Files In Files Out VHDL Simulation Test Bench Image Reader RGB 2 YCbCR Image Writer

  41. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory VHDL RGB2YCbCR result RGB image YCbCr image

  42. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Image Reader RGB 2 YCbCR Image Writer Files In Files Out Files Out Comparison between MATLAB & VHDL RGB2YCbCr results Test Bench main RGB 2 YCbCr read file write file

  43. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Comparison between MATLAB & VHDL RGB2YCbCr results MATLAB YCbCr image VHDL YCbCr image

  44. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Files In Files Out VHDL Simulation Test Bench Image Reader RGB 2 YCbCR YCbCR 2 RGB Image Writer

  45. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Comparison betweenMATLAB & VHDL results Original RGB image RGB image after VHDL conversion to YCbCr And back to RGB

  46. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  47. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Top Hierarchy Block Diagram Local Bus External ddrII Memory interface ck_a Gidel’s block clk0 pll4ddrII ck_b clk clk1 user_pll clk_plus top_if clk_minus DVI input DVI Output idck_tx odck_rx Clk Clk RX TX data_tx qe_rx data_out data_in 24bit 24bit 24bit 24bit 12bit 24bit 1 1 1 de_tx de_rx data_en_out data_en_in hsync_rx hsync_out hsync_tx hsync_in vsync_rx vsync_in vsync_out vsync_tx DVI_interface_2rx RGB2YCbCr block1 YCbCr2RGB DVI_interface_2tx i2c and control i2c and control

  48. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Development Stages • Background • Design • Coding • Simulation • Integration & Implementation

  49. THE END! But not before…

  50. DEMONSTRATION! DEMONSTRATION! DEMONSTRATION!  …Lets Go …

More Related