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Weekly Report

Weekly Report. Renjie Chen Supervisor: Shadi A. Dayeh. Summary. In the past week, I was working on the project of high-density neural probes. There were some problems in the fabrication process, related to the nickel silicide bonding and Si RIE/ICP etching.

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Weekly Report

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  1. Weekly Report Renjie Chen Supervisor: Shadi A. Dayeh

  2. Summary • In the past week, I was working on the project of high-density neural probes. • There were some problems in the fabrication process, related to the nickel silicide bonding and Si RIE/ICP etching. • My target was to: (1) modify the nickel silicide bonding conditions (2) test new metal stacking layers (3) push new samples ready for neural culture/measurement

  3. Processing Flow Problems to solve * Process designed by Prof. Shadi and Dr. Yoontae, and figures adapted from Dr. Yoontae’s presentation

  4. NiSix Bonding Modification 1st Problem: Possible Reason Ti/Pd/Ti/Ni = 30/60/30/400 nm Step height = 640 nm Possible Solutions Ti/Ni/Ti/Ni = 30/50/30/350 Ti/Ni/Ti/Ni = 30/50/30/350 Step height = 570 nm Ti/Ni/Ti/Ni = 30/350/30/50 nm Step height = 870 nm

  5. 2nd Problem: Possible Reason Possible Solutions • Shorten the Bonding time or lower the bonding temperature to have sufficient Ni remained. • Try multiple Metal layer stacking. Previous metal stacking: Ti/Pd/Ti/Ni = 30nm/60nm/30nm/400nm New metal stacking: Ti/Pd/Ti/Ni/Ti/Ni = 30nm/60nm/30nm/200nm/30nm/200nm Ni tape Nickel silicide

  6. Ti/Pd/Ti/Ni = 30nm/60nm/30nm/400nm Edge

  7. Ti/Pd/Ti/Ni/Ti/Ni = 30nm/60nm/30nm/200nm/30nm/200nm Edge

  8. Ti/Pd/Ti/Ni/Ti/Ni = 30nm/200nm/50nm/50nm Metal Stacking

  9. Plan 1. Samples send back to UCSD for thinning/pillar etching 7 Samples with old metal stacking (Ti/Pd/Ti/Ni) finished --5samplesbondedwith90umSi, for Si thinning -> send back -- 2 samples bonded with 10um Si, for pillar etching -> directly use for device 9Samples with new metal stacking (Ti/Pd/Ti/Ni/Ti/Ni) in preparation --7samplesto be bondedwith90umSi, for Si thinning -> send back -- 2 samples to be bonded with 10um Si, for pillar etching -> directly use for device 2. During waiting for samples coming back -- work on Ni-InGaAs project --Cory’s EBL sample, may take some time to calibrate the off-set -- Farid’sPhotomask has finished, will be mailed together with my samples

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