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High Density FPGAs

High Density FPGAs. Xilinx High Density FPGA Families. XC4000EX XC4000XL XC4000XV Virtex. The Largest, Fastest FPGAs in the World. High Density FPGAs. Same Basic Architecture as 4KE (Spartan) New Fabrication Process New Power Supplies More Logic More Logic Cells and I/O Pins

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High Density FPGAs

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  1. High Density FPGAs

  2. Xilinx High Density FPGAFamilies • XC4000EX • XC4000XL • XC4000XV • Virtex The Largest, Fastest FPGAs in the World

  3. High Density FPGAs • Same Basic Architecture as 4KE (Spartan) • New Fabrication Process • New Power Supplies • More Logic • More Logic Cells and I/O Pins • New Packages • Architectural Enhancements • Better Routing, I/O

  4. XC4000 Series FPGA Architecture

  5. Simplified 4K CLB

  6. CARRY LUT CARRY LUT DFF/LATCH DFF/LATCH D SET Q D SET Q CE CE RES RES CARRY CARRY LUT LUT DFF/LATCH DFF/LATCH D SET Q D SET Q CE CE RES RES Simplified Virtex CLB • 4 Logic Cells per CLB • Carry logic (2 independent chains) • 4 FFs/Latches, 2 BUFTs per CLB • 16 bits of SelectRAM per LUT (single / dual-port)

  7. High Density FPGAs Use New Silicon Technology

  8. Xilinx CMOS Process Technology Roadmap 1.2 1 5V 0.8 0.6 Feature Size () 3.3V 0.4 2.5V 0.2 1.8V 1.3V 0 1990 1992 1994 1996 1998 2000 2002 Year Xilinx’ fab partners use FPGAs to drive process

  9. New Fabrication Process 0.5um Process 0.25um UMC Process XC4000EX XC4000XV/Virtex

  10. High Density FPGAs are Faster

  11. High Density ASIC Designs System Frequency 16 The High FPGA Density Arena 14 12 10 8 Percentage of Designs 6 4 2 0 0-10 >200 80-90 20-30 20-30 30-40 40-50 50-60 60-70 70-80 90-100 100-150 150-200 Average Clock Speed (MHz) Dataquest 1997 ASIC Design Starts by Average Clock Speed

  12. High Density FPGAs Have More Logic

  13. High Density Arena Covers ASIC Designs Up To 250,000 Gates 30 25 The High Density Arena 20 15 Percentage of Designs 10 5 0 <10K 10-25K 25-50K 50-100K 100- 150- >250K 150K 250K Design Size (gates) Dataquest 1997 Gate Array Design Starts by Gate Count

  14. High Density FPGAs Require New Power Supplies

  15. 0.35/0.25 FPGA, 5 Volt Compatible I/O 5V • XL/XV accept 5 volt TTL inputs • XL/XV drive standard LVTTL levels • XV has separate I/O & Core Supplies 3.3V 2.5V I/O Supply Core Supply 5V 3.3V XC4000E 5V Core 5V I/O XC4000XV 2.5V Core 3.3V I/O XC4000XL 3.3V Core 3.3V I/O 3.3V 3.3V Meets TTL Levels

  16. High Density FPGAs Require new Packages

  17. Xilinx Pioneers FPGA Packages PQFPs & VQFPs BGA 3000 • First to use PQFP & VQFP • First to use BGA & SBGA (Super BGA) • Investigating flip-chip today for higher integration solutions 1000 Flip-chip Package Pins SBGA 100 1992 1994 1996 1998 2000 2002 Year

  18. High Density FPGAs Have Increased Routing • Most of the silicon area is used for interconnect

  19. High Density FPGAs Require More Interconnect • Larger designs require more and longer interconnects • Large designs preclude hand placement • More interconnect resources enable higher performance designs • Interconnect delay dominates path • 50% - 80% of total path delay • More interconnect enables faster routing

  20. XC4000X Interconnect Hierarchy

  21. CARRY CARRY 3-STATE BUSSES SWITCH MATRIX CLB 2 LCs 2 LCs CARRY CARRY Virtex Interconnect • 4 LCs per CLB • Fast local routing within CLBs • General purpose routing between CLBs • Hierarchical interconnect is scaleable, and has predictable fast performance

  22. High Density FPGAs Have Clock Distribution Enhancements • EX/XL/XV • 8 Global Low Skew Clock Buffers - BUFGLS (for Logic) • 8 Global Early Clock Buffers BUFGE (for I/O) • Virtex • Very Low Skew Clock Buffers • On-Chip DLL to remove clock delay

  23. XC4000X Global Early Buffers Left and Right (#1 shown) Top and Bottom (#8 shown)

  24. PAD PAD IOB CLB to internal logic FF D Q > OFD D Q > Data BUFGLS 2.8ns+3.5ns 2.8ns 5.5ns Clock BUFGE XC4000X: Faster Clock-to-Out • Use of BUFGE #1,2,5,6 allows reduction of clock to out delay by up to 2-3ns for XC4085XL-09 • Tgls(XC4085) = 5.5ns Tickof = 9.0ns • Tge(from TRCE) = 2.8ns Tickeof = 6.3ns

  25. Virtex Clocking and PLL • Ultra-low skew, fast clocks • 66 MHz PCI performance without PLL • Phase-Locked Loop (PLL) • Compensate for clock network delay • Clock multiplication • Duty cycle correction • Reference output for system timing

  26. High Density FPGAs Have IOB Enhancements • EX/XL/XV • Fast Capture Latch (FCL) in IOB • Output Multiplexer (OMUX) in IOB • Virtex • Registered Output Enable • Support for non-TTL Signaling

  27. PAD PAD XC4000X Fast Capture Latch • Additional latch on input driven by output’s clock signal • Allows capture of input by very fast clock • Followed by standard I/O storage element for synchronization to internal logic ILFFX FCL D Q G IFD D Q > to internal logic Data BUFGE Clock BUFGLS

  28. Virtex IOB DFF/LATCH D Q • Fast I/O drivers • Registered input, output, 3-state enable control • Programmable slew rate, pull-up, input delay, etc. CE S/R DFF/LATCH D Q CE PAD S/R DFF/LATCH D Q CE S/R

  29. Hierarchy of RAM Registers Distributed SRAM (in 4K CLB) Block RAM (Virtex Only) External RAM SDRAM, SDRAM FIFOs (First In First Out Memories) System RAM (Via PCI BUS) High Density FPGAs Need more RAM

  30. 4KE/X Single-Port RAM

  31. 4K E/X Dual-Port RAM

  32. RAMB4 WEA ENA CLKA ADDRA DINA DOA DOB Virtex Block RAM • Configure as: 4096 bits with variable aspect ratio • 8-30 blocks per device (20K-200K logic gate devices) • True dual-port, fully synchronous operation • Cycle time <10 ns • Flexible block RAM configuration • 5 blocks: 2K x 10 video line buffer • 1 block: 512 x 8 ATM buffer (9 frames) • 4 blocks: 2K x 8 FIFO • 9 blocks: 4K x 9 FIFO with parity WEB ENB CLKB ADDRB DINB

  33. High Density FPGAs have Increased Complexity • Bigger Designs • Simulation/Error analysis is more difficult • New functions in FPGAs • DSP type Functions • Data Processing Functions • Memory • CPUs

  34. High Density FPGAs have new design entry methods • ASIC toolkit • Verilog / VHDL design entry • Logic is purchased and Integrated as LogicCores (example PCI) • Integration / Modification still required • Simulation and Verification required • Software algorithm/program may be source of design

  35. New Problems when using High Density FPGAs • New Tools • M1 is required for for EX/XL/XV • Tools are slower for bigger FPGAs • Power must be managed • Can’t be ignored any longer • Heatsinks, Fans may be necessary • Parts are physically bigger and have more pins such as the BG560 package • BGA Packages require higher tech FAB

  36. Team Design • Typical Productivity is 10K gates/month • 250K design will take over 2 years !!! • A Single High Density FPGA Design may require a team of designers. • FPGA designers need same skills and tools as ASIC and SW designers. • Board and System level simulation may be required

  37. Web Resources • Crossroads http://web/ • Site Search http://web:7000/cgi-bin/search.cgi/x-catalog:/web:7000/Crossroads • FTP site ftp://ftp.xilinx.com/pub/ • High Density Marketing Home page http://web/corpmktg/whoswho/dsfpga.htm • Marketing Presentationshttp://web/corpmktg/custpres/ • FAE Newsgroup news:xilinx.fae.questions

  38. Collateral Resources • Datasheets http://www.xilinx.com/partinfo/db96.htm • Application Notes http://www.Xilinx.com/apps/appsweb.htm • Speed Files ftp://ftp.xilinx.com/pub/swhelp/speed_files/ • BSDL(Boundary Scan) http://www.xilinx.com/support/techsup/ftp/htm_index/sw_bsdl.htm • IBIS Models(I/O Characteristics) ftp://ftp.xilinx.com/pub/swhelp/ibis/ • Engineering Presentations http://web:80/corpcomm/distribution/engineer.htm • High Density Product Availability Guide http://web/corpmktg/home/psu/xc4000ex/4kexsil.htm

  39. Technical Data Sources • Product availability http://web/corpmktg/home/psu/newpsu.htm • Competitive Benchmark Serverhttp://icarus/cgi-bin/getmag2 • Lab Reportshttp://web/~yiding/fpgalab/labreports/labreports.html • Packaging Data http://web/aprfa/pkg/index.htm • The Pinout Page http://web/prodtech/pins/index.html • The Software Page http://web/randd/software/

  40. High Density Marketing • XL/XV Marketing • David Squires • Barry Chaffin • Andrew Girardi • Virtex Marketing • Bruce Jorgens • Applications Engineering • Al Graf • Brad Taylor http://web/~blt/ • Hernan Saab

  41. High Density Performance Estimation • Need to Know • Design Size - 4LUTS or Gates or Registers • I/O pins - Number of pins, Speed • Target System Frequency • Power Requirements • Memory Requirements

  42. Capacity • 1 Logic Cell = 1 Input LUT+ 1 Register + Carry • 1 Logic Cell = 8-25 system gates

  43. I/O Pins

  44. Typical Power/FPGA • Based on App Brief #XBRF014 http://www.xilinx.com/xbrf/xbrf014.pd • Frequency = 50 MHZ, 70% Fill,@ 15% toggle rate, • 100% of I/O Pins@ 25% I/O toggle rate • 50pf I/O Loading

  45. Peak Power could be 4X Typical Power • 50 MHz -> 100 MHz, • 70% Fill -> 100%, • 15% toggle rate -> 100%toggle rate, • 100% of I/O Pins • pin 25% toggle rate -> 100% toggle rate

  46. Internal FPGA Speed

  47. Application Speed • FPGA Speed depends on FPGA application and design methodology

  48. FPGA Components • Basic Classes of Components • I/O pins • Interconnect • Combinatorial Circuits • State Machines • Multiplexers • AND/OR terms • Math Circuits • Memories

  49. I/O Frequency FPGA1 FPGA1 External DATA FFO D Q > IFF D Q > • Fio(ext) = Maximum I/O Clock frequency • Fio(ext) = 1/(Tckout+ Tsetup) • Full delay inputs (0ns hold) • Fast outputs • Pin to Pin (referenced to external clock pin) Dout Din PAD PAD Internal Clock 2 PAD Internal Clock 1 PAD External Clock

  50. I/O Speed

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