Project Traffic Light Controller Prawat Nagvajara

1. Project Traffic Light ControllerPrawat Nagvajara Goals: To design and synthesize a controller (FPGA) that interfaces with a virtual traffic (java animation). We will design • Handshake protocol • Timer • Finite State Machine

2. Traffic at an Intersection

3. The Setup of The TLC Problem Controller (FPGA)

4. The Remote Site

5. Problem Statement • Design a controller for the virtual traffic scenario – an intersection with no turns • The controller changes the flow of the traffic if there is a car waiting on-red and the traffic flow in the present direction has been longer than a specified duration • Parameters: green-light duration and yellow-light duration • Signals: • To remote site: change_light • From remote site: car_waiting and acknowledge

6. Xilinx FPGA Design Flow • VHDL code and simulation • Synthesis • Mentor Graphics leonardo tool, invoking command, leonardo or • Xilinx Foundation tools: synthesis • Implementation using Xilinx Foundation to FPGA hardware code • Download compiled code (.bit file) to an FPGA demo board

7. User Constraint File - Pins Definition • Associate signals and pins use this project_name.ucf file NET reset LOC = P28; NET car_waiting LOC = P20; NET acknowledge LOC = P24; NET change_sim_light LOC = P70; NET change_real_light LOC = P60; • All signals are active-low • Change_real_light toggles (between ‘0’ and ‘1’) in turn triggers a transition of the physical lights. • Reset for setting the controller to a known state (RedGreen) • In the initial state (RedGreen), Change_real_light is ‘0’

8. Internal Oscillator of XC4000E component osc4 port ( F8M : out std_logic; F500K: out std_logic; F16K : out std_logic; F490 : out std_logic; F15 : out std_logic); end component;

9. Partially Completed VHDL Code • Contains declaration of signals and components • Need to complete the FSM portion • FSM handles the handshake protocol, I.e., change light request and acknowledgement • Contains VHDL code for timer