1 / 14

Power Everywhere POWER5 Processor Update

Explore the cutting-edge advancements in IBM's POWER architecture, from POWER2 to POWER5, and its impact on Mars exploration, space computers, and Department of Defense applications. Discover the revolutionary features of POWER4, POWER5, and POWER5+ processors, setting new standards for scalability, performance, and efficiency in server systems.

miriamb
Download Presentation

Power Everywhere POWER5 Processor Update

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Power EverywherePOWER5 Processor Update Mark Papermaster VP, Technology Development IBM Systems and Technology Group

  2. Servers Desktop Games Embedded POWER : The Most Scaleable Architecture POWER5 POWER4+ POWER4 Binary Compatibility POWER3 POWER2 PPC 970FX PPC 750GX PPC 750FX PPC 750CXe PPC 750 PPC 603e PPC 440GX PPC 440GP PPC 405GP PPC 401

  3. PowerPC is at the heart of the BAE Systems RAD6000 Single Board Computer, a specialized system enabling the Mars Rovers — Spirit and Opportunity — to explore, examine and photograph the surface of Mars. In fact, a new generation of PowerPC based space computers is ready for the next trip to another planet. The RAD750, also built by BAE Systems, is powered by a licensed radiation-hardened PowerPC 750 microprocessor that will power space exploration and Department of Defense applications in the years to come. IBM Powers Mars Exploration

  4. POWER4 Recognition --- January 2002 “… considering system scalability, bandwidth, chip-level multiprocessing, fault tolerance, and performance --- it is impossible to ignore the accomplishments of the IBM POWER4 architecture … “It has … actually met shipment schedules publicized 2 years ago; and generally lived up to the promise.” – Kevin Krewell Senior Analyst, Microprocessor Report

  5. POWER4: Foundation for Systems Value POWER4 High-end Mid-range, Low-end First dual-core microprocessor

  6. 2004-5 2005-6 2006-7 POWER5 POWER5+ POWER6 65 nm 90 nm 130 nm >> GHz Core >> GHz Core Ultra high frequency cores > GHz Core > GHz Core 1.2-1.9 GHz Core 1.2-1.9 GHz Core 1.0-1.3 GHz Core 1.0-1.3 GHz Core Shared L2 L2 caches Distributed Switch Advanced System Features Distributed Switch Shared L2 Shared L2 Simultaneous multi-threading Sub-processor partitioning Dynamic firmware updates Enhanced scalability, parallelism High throughput performance Enhanced memory subsystem Distributed Switch POWER Server Roadmap 2001-2 2002-3 POWER4 POWER4+ 130 nm 180 nm Shared L2 Distributed Switch Reduced size Lower power Larger L2 More LPARs (32) Chip Multi Processing - Distributed Switch - Shared L2 Dynamic LPARs (16) Autonomic Computing Enhancements

  7. POWER5™ Objectives Build on POWER4 base • Maintain binary and structural compatibility • Enhance and extend multiprocessor scalability • Continue superior performance • Provide breakthrough virtualization server flexibility • Deliver power efficient design • Enhance reliability, availability, serviceability attributes

  8. POWER5 Systems --- A New Standard • Second generation dual core chip • Intelligent 2-way SMT • Power management with no performance impact • 130 nm lithography • 276M transistors • 8 layers of metal • Micropartitioning • Up to 64 physical processors,1280 virtual processors per system • Virtual I/O • Virtual LAN • Eight way SMP looks like 16-way to software • All that’s needed is DIMMs and I/O • 95 mm on a side • Performance equivalent to >4 p690 MCMs

  9. Reduced L3 Latency Number of chips cut in half Faster access to memory Mem Ctl Mem Ctl Modifications to POWER4 to create POWER5 P P P P L2 L2 Larger SMPs Fab Ctl Fab Ctl L3 Cntrl L3 Cntrl L3 L3 Memory Memory

  10. Simultaneous Multi-Threading FX0 FX1 FP0 FP1 LS0 LS1 Thread 0 active Thread 1 active BRX CRL Simultaneous Multi-Threading in POWER5 • Each chip appears as a 4-way SMP to software • Processor resources dynamically optimized for enhanced multithreading performance • Dynamic switching between single and multithreaded mode

  11. Dynamic Power Management Reduces power automatically – no program intervention required and no performance impact Two components: switching power and leakage power • Switching power reduction: • Extensive fine-grain, dynamic clock-gating • Leakage power reduction • Minimal use of low Vt devices

  12. No Power Management Dynamic Power Management Single Thread Photos taken with thermal sensitive camera while prototype POWER5 chip was undergoing tests Simultaneous Multi-threading Simultaneous Multi-threading with dynamic power management reduces power consumption below standard, single threaded level

  13. Reliability, Availability, Serviceability • POWER4 drove unscheduled outages to near zero • POWER5 designed to significantly reduce scheduled outages • Adds dynamic firmware upgrades • Allows for concurrent CEC maintenance • … while at the same time enhancing basic reliability • Full ECC on chip interconnections including address and tag • Additional centralized resource redundancy

  14. POWER5: Delivers system performance and value through leadership technology Highest Value / Lowest Risk Superior Availability Superior Flexibility Lower TCO Higher Performance Leading Technology

More Related