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Processor Power Reduction

Outline. BackgroundWhy is power consumption such a big issue?What can be done?Project ObjectiveLiterature ReviewRelated WorkDrawbacks in approaches presented in the literatureProject ProposalProject Schedule. Why is Power Consumption such a big concern?. Performance vs PowerBattery life ? a

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Processor Power Reduction

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    1. Processor Power Reduction Emily Chan Supervisor: Annie Guo

    2. Outline Background Why is power consumption such a big issue? What can be done? Project Objective Literature Review Related Work Drawbacks in approaches presented in the literature Project Proposal Project Schedule

    3. Why is Power Consumption such a big concern? Performance vs Power Battery life ? a bottleneck of portable equipments Beginning to reach the limits of conventional air cooling techniques SAVE OUR WORLD !!! SAVE OUR MONEY !!!

    4. What is the problem? Different applications vary in: degrees of instruction-level parallelism (ILP) branch behaviors memory access patterns ?Data path resources are not optimally utilized by all applications or even at all times within an application

    5. GOLDEN DESIGN RULE “A good design strategy should be flexible enough to dynamically reconfigure available resources according to the program’s needs” [1].

    6. Project Objective To show the potential in power saving through dynamically reconfiguring the issue logic as well as the functional units To maximize the flexibility for a system to carry out reconfigurations in an effective and efficient manner To minimize the impact on performance

    7. Related Work Three previous schemes presented: Two of these use FIFOs ? both focus on the dynamically reconfiguration of issue logic (i.e. issue queue structure) Divide into Integer and Floating Point (FP) Pipelines ? focus on the dynamically reconfiguration of pipeline clusters

    8. Properties of the 2 FIFO Schemes Issue queue divided into several FIFOs Only head of each FIFO is “visible” to the selection/arbitration logic H/W performance monitors provide feedback on a cycle-window basis ? CPU switches among different operating modes

    9. Scheme# 1 using FIFOs A FIFO is completely disabled when underutilized All signals associated are completely disabled ? more power saving!! Shrink Issue queue size ? limit exposure to ILP ? very poor performance for FP benchmarks

    10. Scheme# 2 using FIFOs The number and size of FIFOs are reconfigured simultaneously Size of Issue queue remains constant ? Better exposure to potential ILP !! Not all signals of the “invisible” entries are disabled ? wasting power !!

    11. Integer & FP Clusters Two clusters of data path resources: FP Cluster and Integer Cluster Integer Cluster further divided into: Upper Integer Cluster & Lower Integer Cluster H/W Performance Monitor provide feedback on cycle-window basis ? disable part of the Integer pipeline and/or the entire FP pipeline Also use trigger events to switch among operating modes e.g. a FP instruction is fetched

    12. Pipeline Organization More flexibility in reconfiguring the pipeline due to different types of instructions Associated signals are disabled when a cluster is disabled ? power saving !! All instructions within an enabled cluster are “visible” to the selection logic ? power inefficient !! Shrinking in issue queue size ? limit exposure to ILP

    13. Summary of Drawbacks The two FIFOs Schemes: ? lack of flexibility in reconfiguring the data path according to the type of benchmarks FP & Integer Cluster Scheme: ? all entries are “visible” to the selection logic at all times even when they are not ready ALL Schemes: ? Computed results are broadcast to every entries in the issue queue even when these results are useless for instructions that are ready

    14. Project Proposal ~ Step 1 Divide the pipeline into two clusters: Integer Cluster & FP Cluster Within each cluster: issue queue and corresponding functional units Disable part/all of a pipeline cluster according to the feedback from H/W Performance Monitors as well as some trigger events Provides the system with greater flexibility when handling different types of applications

    15. Proposed Pipeline Organization

    16. Project Proposal ~ Step 2 Divide the issue queue in each cluster into several FIFOs Classify the FIFOs into two categories: Ready & Non-Ready FIFOs H/W Performance Monitors feedback: Size and Number of FIFOs of each issue queue are reconfigured simultaneously ? issue queue size remains constant

    17. Proposed Issue Queue Structure Non-ready instructions are hidden from the selection logic ? power efficient Exposure to potential ILP is maximized by maintaining the size of issue queue at all times Broadcasting of computed results are restricted to non-ready instructions only ? power efficient

    18. Thoughts at this stage Independencies in reconfigurations Simplify implementation Provide more flexibility H/W Performance Monitors & trigger events: extract from previous papers and some new ones are added Simple counters and comparators ? power consumption neglected Benchmarks: Spec95 Ease in comparing results with previous papers Tool: SimpleScalar Power Estimates: extrapolate from available Alpha 21264 power estimates

    19. Project Schedule

    20. Conclusion Current Trend: Power issue must be considered in the design phase of a processor Effective and Efficient usage of resources Tasks to be carried out in proposed project are: Dividing the pipeline into two clusters: Integer and FP clusters More control over power saving due to different types of instructions Partition the issue queue into FIFOs Non-ready instructions are kept hidden; selection/arbitration signals disabled ? power saving Classify FIFOs into Ready and Non-Ready types Broadcasting of results are restricted only to the Non-Ready FIFOs ? power saving The combinations of these techniques eliminate the problems with previous implementations shown ? better performance in power savings is expected.

    21. References [1] Yu Bai and R. Iris Bahar. A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. Division of Engineering, Brown University. [2] K. Wilcox and S. Manne. Alpha processors: A history of power issues and a look to the future. In Cool-Chips Tutorial, November 1999. Held in conjunction with the 32nd International Symposium on Microarchitecture. [3] R. Maro, Y. Bai, and R. I. Bahar. Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors. In Workshop on Power-Aware Computer Systems, November 2000. Held in conjunction with the International Conference on Architectural Supportfor Programming Languages and Operating Systems (ASPLOS). [4] R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th InternationalSymposium on Computer Architecture, July 2001.

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